ACD2206 Datasheet, PDF (9/20 Pages) ANADIGICS, Inc – CATV/TV/VIDEO DOWNCONVERTER WITH DUAL SYNTHESIZER

ACD2206
Main Divider Programming
The main divider register for each synthesizer
consists of seven A counter bits, eleven B counter
bits, two program mode bits and the two register
select bits, as shown in Table 10. The main divider
divide ratio, N, is determined by the values in the A
and B counters. The eleven B Counter bits and
allowed values are shown in Table 11, and the seven
A Counter bits and allowed values are shown in
Table 12. Note that there are some limitations on
the ranges of the values for each counter.
Pulse Swallow Function
The VCO output frequency for the local oscillator is
computed using the following equation; the
variables are defined in Table 13:
fVCO = N x fOSC/R, where N = [(P x B) + A]
MSB
Table 10: Main Divider Registers
LSB
22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
Program
Mode
B Counter
A Counter
Select
C C B B B B B B B B B B BAAAAAAA S S
2 1 11 10 9 8 7 6 5 4 3 2 1 7 6 5 4 3 2 1 2 1
Table 11: Main Divider B Counter Bits
VALUE OF B B B B B B B B B B B B
COUNTER 11 10 9 8 7 6 5 4 3 2 1
3
000000000 11
4
00000000 100
-
-----------
2047
11111111111
Notes:
B > A, Divide ratios less than 3 are prohibited.
Table 12: Main Divider A Counter Bits
VALUE OF A A A A A A A A
COUNTER 7 6 5 4 3 2 1
0
0000000
1
000000 1
-
-------
127
Notes:
B > A, A < P
1111111
Table 13: Variable Definitions
VAR
DEFINITION
fVCO
Desired output frequency of external voltage
controlled oscillator (VCO)
B Divide ratio of B counter (3 to 2047)
A Divide ratio of A counter (0 < A < P, A < B)
fOSC
Frequency of external reference crystal or
oscillator
R Divide ratio of R counter (3 to 32767)
P Preset modulus of prescalar (P = 64)
PRELIMINARY DATA SHEET - Rev 1.0
9
10/2003