ACD2206 Datasheet, PDF (11/20 Pages) ANADIGICS, Inc – CATV/TV/VIDEO DOWNCONVERTER WITH DUAL SYNTHESIZER

ACD2206
For the up converter, the 4 MHz crystal oscillator frequency and the 250 KHz phase detector comparison
frequency are used to yield RPLL1 = 4 MHz / 250 KHz = 16, and so the bit values for the up converter R counter
are RPLL1 = 000000000010000.
Calculation of Main Divider Values
The values for the A and B counters are determined by the desired VCO output frequency for the local
oscillator and the phase detector comparison frequency:
N = f_VCO / f _PD
B = trunc(N / P)
A = N - (B x P)
The down converter local oscillator frequency will be 1087.75 MHz - 45.75 MHz = 1042 MHz in this example.
The main divider ratio for the down converter, then, is NPLL2 = 1042 MHz / 62.5 KHz = 16672. Since P = 64 in the
ACD2206, BPLL2 = trunc(16672 / 64) = 260, and APLL2 = 16672 - (260 x 64) = 32. These results give bit values of
BPLL2 = 00100000100 and APLL2 = 0100000 for the B and A counters.
The up converter local oscillator frequency will be 499.25 MHz + 1087.75 MHz = 1587 MHz in this example.
Therefore, NPLL1 = 1587 MHz / 250 KHz = 6348, BPLL1 = trunc(6348 / 64) = 99, and APLL1 = 6348 - (99 x 64) = 12.
These results give bit values of BPLL1 = 00001100011 and APLL1 = 0001100 for the B and A counters.
Phase Detector Polarity
Assuming the VCO for the up converter has a negative slope, the phase detector polarity for PLL1 should be
negative, and D1PLL1 = 1. If the VCO for the down converter has a positive slope, the phase detector polarity for
PLL2 should be positive, and D1PLL2 = 0.
In summary, for this example, the four register programming words are shown in Tables 16 and 17:
Table 16: PLL1 and PLL2 Reference Divider Register Bits
MSB
for Synthesizer Programming Example
LSB
22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
Program
Mode
Main Divider B Counter
Main Divider A Counter Select
C C B B B B B B B B B B BAAAAAAA S S
2 1 11 10 9 8 7 6 5 4 3 2 1 7 6 5 4 3 2 1 2 1
0 0 0 0 1 0 0 0 0 0 1 0 0 0 100000 0 1
0 0 0 0 0 0 1 1 0 0 0 1 1000 1100 1 1
Table 17: PLL1 and PLL2 Main Divider Register Bits
MSB
for Synthesizer Programming Example
LSB
22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
Program Mode
Reference Divider R Counter
Select
DDDDDRRRRRRRRRRRRRRRSS
5 4 3 2 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 2 1
0000 100000000 100000000
000000000000000 10000 10
PRELIMINARY DATA SHEET - Rev 1.0
11
10/2003