ACD2206 Datasheet, PDF (10/20 Pages) ANADIGICS, Inc – CATV/TV/VIDEO DOWNCONVERTER WITH DUAL SYNTHESIZER

ACD2206
Programmable Modes
Each register contains bits set aside for programming
different modes of operation in the synthesizers.
Currently, the only programmable mode is the polarity
of the phase detector in each of the synthesizers. Bit
D1 in each reference divider register controls this
feature. Bits D2 through D5 in the reference divider
registers and bits C1 and C2 in the main divider
registers are reserved for future use, and have no
current function. They can be set either high or low
without affecting synthesizer performance.
Setting Phase Detector Polarity
Table 14 shows how bit D1 of each reference divider
register controls the polarity of the phase detector
associated with each PLL. The correct setting is
determined by using Table 15 and Figure 10.
Table 14: Phase Detector Polarity Bit
SS
D
21
1
00
PLL2 Phase Detector Polarity
10
PLL1 Phase Detector Polarity
Figure 10: VCO Characteristics
(1)
Table 15: Phase Detector Polarity Selection
PHASE
VCO
D DETECTOR CHARACTERISTICS
1 POLARITY
(SEE FIGURE 12)
0 Negative
curve (2)
1
Positive
curve (1)
VCO OUTPUT
FREQUENCY
(2)
VCO INPUT VOLTAGE
Synthesizer Programming Example
The following example for programming the two synthesizers in the ACD2206 details the calculations used to
determine the required value of each bit in all four registers:
Requirements
Desired CATV input channel: “HHH” - 499.25 MHz picture carrier (501 MHz digital channel center frequency)
(Second) IF picture carrier output frequency: 45.75 MHz (44 MHz digital channel center frequency)
First IF frequency: 1087.75 MHz
Phase detector comparison frequency for down converter (also tuning increment): 62.5 KHz
Phase detector comparison frequency for up converter: 250 KHz
Crystal reference oscillator frequency: 4 MHz
Calculation of Reference Divider Values
The value for each reference divider is calculated by dividing the reference oscillator frequency by the desired
phase detector comparison frequency:
R = fOSC / fPD
For the down converter, the 4 MHz crystal oscillator frequency and the 62.5 KHz phase detector comparison
frequency are used to yield RPLL2 = 4 MHz / 62.5 KHz = 64, and so the bit values for the down converter
R counter are RPLL2 = 000000001000000.
10
PRELIMINARY DATA SHEET - Rev 1.0
10/2003