A82DL32X4T Datasheet, PDF (57/60 Pages) AMIC Technology – Stacked Multi-Chip Package (MCP) Flash Memory and SRAM, A82DL32x4T(U) 32 Megabit (4Mx8 Bit/2Mx16 Bit) CMOS 3.3 Volt-only, Simultaneous Operation Flash

A82DL32x4T(U) Series
ERASE AND PROGRAMMING PERFORMANCE
Parameter
Typ. (Note 1) Max. (Note 2) Unit
Comments
Sector Erase Time
Chip Erase Time
0.7
15
sec Excludes 00h programming
prior to erasure (Note 4)
27
sec
Byte Programming Time
5
150
µs
Word Programming Time
7
Accelerated Word/Byte Programming Time
4
210
µs
Excludes system-level
120
µs _{overhead (Note 5)}
Chip Programming Time
Byte Mode
9
27
sec
(Note 3)
Word Mode
6
18
sec
Notes:
1. Typical program and erase times assume the following conditions: 25°C, 3.0V VCC_F, 10,000 cycles. Additionally,
programming typically assumes checkerboard pattern.
2. Under worst case conditions of 90°C, VCC_F = 2.7V, 100,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
program faster than the maximum byte program time listed.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the four-bus-cycle command sequence for programming. See Table 12
for further information on command definitions.
6. The device has a minimum erase and program cycle endurance of 10,000 cycles.
FLASH LATCH-UP CHARACTERISTICS
Description
Input Voltage with respect to VSS on all I/O pins
VCC_F Current
Input voltage with respect to VSS on all pins except I/O pins
(including A9, OE and RESET )
Includes all pins except VCC_F. Test conditions: VCC_F = 3.0V, one pin at time.
Min.
-1.0V
-100 mA
-1.0V
Max.
VCC_F+1.0V
+100 mA
12.5V
DATA RETENTION
Parameter
Minimum Pattern Data Retention Time
Test Conditions
Min
150°C
10
125°C
20
Unit
Years
Years
PRELIMINARY (August, 2005, Version 0.0)
56
AMIC Technology, Corp.