A49LF040 Datasheet, PDF (14/31 Pages) AMIC Technology – 4 Mbit CMOS 3.3Volt-only Low Pin Count Flash Memory

Figure 3: System Memory Map and Device Memory Map for A49LF040
A49LF040
Block 7
(64K Bytes)
Block 6
(64K Bytes)
Block 5
(64K Bytes)
Block 4
(64K Bytes)
Block 3
(64K Bytes)
Block 2
(64K Bytes)
Block 1
(64K Bytes)
Block 0
(64K Bytes)
Device Memory
07FFFF
070000
06FFFF
TBL#
060000
05FFFF
050000
04FFFF
040000
03FFFF
030000
02FFFF
WP#
for Block 6 ~ 0
020000
01FFFF
010000
00FFFF
000000
A49LF040
Table 11: Software Data Protection Command Definition
Command
Bus
Cycles
1^st Cycle⁽¹⁾
Addr⁽²⁾ Data
2^nd Cycle
Addr Data
3^rd Cycle
Addr Data
4^th Cycle
Addr Data
5^th Cycle
Addr Data
6^th Cycle
Addr Data
Block Erase
Chip Erase⁽³⁾
6
YYYY 5555H AAH YYYY 2AAAH 55H YYYY 5555H 80H YYYY 5555H AAH YYYY 2AAAH 55H
BA⁽⁴⁾
30H/50H⁽⁵⁾
6
YYYY 5555H AAH YYYY 2AAAH 55H YYYY 5555H 80H YYYY 5555H AAH YYYY 2AAAH 55H YYYY 5555H 10H
Byte Program
4
YYYY 5555H AAH YYYY 2AAAH 55H YYYY 5555H A0H
PA⁽⁶⁾
PD⁽⁶⁾
Product ID Entry
Product ID Exit⁽⁷⁾
Product ID Exit⁽⁷⁾
3
YYYY 5555H AAH YYYY 2AAAH 55H YYYY 5555H 90H
1
XXXX XXXXH F0H
3
YYYY 5555H AAH YYYY 2AAAH 55H YYYY 5555H F0H
Notes:
1. LPC Mode uses consecutive Write cycles to complete a command sequence; A/A Mux Mode uses consecutive bus cycles to complete a
command sequence.
2. YYYY = A[31:16]. In LPC mode, during SDP command sequence, YYYY must be within memory address range specified in Table 5. In A/A
Mux mode, YYYY can be V_IL or V_IH, but no other value.
3. Chip erase is available in A/A Mux Mode only.
4. BA: Block Erase Address.
5. Either 30H or 50H are acceptable for Block Erase.
6. PA: Program Byte Address; PD: Byte data to be programmed.
7. Both Product ID Exit commands are equivalent.
PRELIMINARY (August, 2004, Version 0.1)
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AMIC Technology, Corp.