AMIS-710401 Datasheet, PDF (7/9 Pages) AMI SEMICONDUCTOR – 400dpi CIS Module

AMIS710401-A4: 400dpi CIS Module
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Data Sheet
11.0 Timing Characteristics at 25°C
The timing characteristics at 25°C for the I/O clocks are shown in Figure 5 and their definitions are detailed in Table 9.
Figure 5: Module Timing Diagram
Table 9: Timing Definitions
Item
Symbol
Min.
Typ.
Max.
Units
Clock cycle time
to
0.182
2.9
µs
Clock pulse width
tw
46
730
ns
Clock duty cycle
Prohibit crossing time of the SP⁽¹⁾
25
tprh
84
75
%
ns
Data setup time
tds
86
ns
Data hold time
tdh
94
ns
Signal delay time
tdl
50
ns
Signal settling time
tsh
100
ns
Note:
(1) "Prohibit crossing of the SP", tprh, is to indicate that the start pulse should not be active high between two consecutive low going clock pulses. All falling clock
edges under an active high start pulse loads the internal shift register, therefore the start pulse must be active over only one falling clock edge. A high start pulse
crossing over any rising clock edges are ignored by the shift register. One simple way to ensure that the start pulse will not be actively high for any two consecutive
falling clock edges is to generate the start pulse on a rising clock edge and terminate it on the following rising clock edge.
AMI Semiconductor – Jun. 06, M-20589-001
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