AMIS-710205 Datasheet, PDF (7/9 Pages) AMI SEMICONDUCTOR – 200dpi CIS Modules

AMIS-710205-A4/AMIS-710206-A4: 200dpi CIS Modules
Data Sheet
11.0 Switching Characteristics (25°C)
The switching characteristics at 25°C for the I/O clocks are shown in Figure 4. Each switch timing characteristic for each waveform is
represented by its symbolic acronym. Each corresponding switching time is defined in Table 9.
Figure 4: Module Timing Diagram
Note: Only one video output is shown because all four videos have identical electrical characteristics. The only physical difference between the outputs is in the Section 4
output, VOUT4. Section 4 has only six sensor chips; hence, its active scan is shorter by 64 pixels (see Figure 4).
Table 9: Timing Symbol’s Definitions and Timing Values
Item
Symbol
Min.
Typ.
Max.
Units
Clock cycle time
to
0.20
4.0
µs
Clock pulse width
tw
50
ns
Clock duty cycle
25
75
%
Prohibit crossing time of Start
tprh
0
ns
Pulse⁽¹⁾
Data setup time
tds
20
ns
Data hold time
tdh
0
ns
Signal delay time
tdl
20
ns
Signal settling time
tsh
100
ns
Note:
(1) "Prohibit crossing of start pulse" is used to indicate that the start pulse should not be active high between any two consecutive clock pulses; specifically, between
two consecutive low going clock pulses (see the Figure 4). All falling clock edges under an active high start pulse load the internal shift register, therefore the start
pulse must be active over only one falling clock edge. A high start pulse over all rising clock edges is ignored by the shift register. One simple way to ensure that
the start pulse will not be actively high during two consecutive falling clock edges is to generate the start pulse on a rising clock edge and terminate it on the
following rising clock edge.
AMI Semiconductor – Aug. 06, M-20608-001
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