AMIS-42700 Datasheet, PDF (7/16 Pages) AMI SEMICONDUCTOR – Dual High-Speed CAN Transceiver

AMIS-42700 Dual High-Speed CAN Transceiver
Preliminary Data Sheet
7.4 Feedback Suppression
To provide proper function a feedback suppression must be included. This circuit replaces the reception of a dominant bit detected
by the receiving section with a recessive bit if the corresponding transmitter is active.
The feedback suppression must be activated immediately after the transmitter is requested to drive, i.e. before the receiver detects
the dominant state at the bus. After deactivating the transmitter, the feedback suppression must stay active long enough to
guarantee that the corresponding receiver has sufficient time to change its state from dominant to recessive.
Including the feedback, suppression is possible because a transmitter becomes active if the other bus system or Tx0 is in the
dominant state, so the reception of a dominant bit is already realized and need not be done additionally by this receiving section.
Without feedback suppression the whole system would stay constantly in the dominant state after the occurrence of one dominant
bit.
The logic is implemented in such a way that the suppression blocks in the two busses work independently of each other, and are
identical so that both busses have the same priority. Furthermore the oscillation or single pulsing, that could occur at the dominant
to recessive edge when the transceiver has received acknowledges from both busses, is avoided with this implementation.
If both buses are driven externally and go from dominant to recessive with some delay between each other, no spurious pulses are
seen at RINT and Rx0. However, it is possible to have the driving section of one bus going active while that bus is still driven
externally. To minimize the chance of this condition, an additional delay of typical 50ns is added that blocks the requirement to
drive the driving section after the bus is forced externally from dominant to recessive.
7.5 Logic Unit and CAN Controller Interface
The central logic unit provides data transfer from/to the digital interface to/from the two busses and from one bus to the other bus.
Digital input stages convert the input voltage at Tx0 and TEXT into a logical value for the logic unit. All digital inputs, including
ENBx, have an internal pull up resistor to ensure a recessive state when the input is not connected or is accidentally interrupted.
Output stages convert the logical value provided by the logic unit into voltages corresponding to the input signal specification of the
CAN controller at Rx0 and RINT. A dominant state on the bus line is represented by a low-level at the digital interface, a recessive
state is represented by a high-level.
V_ref provides an analog voltage of V_cc/2 as a reference for CAN controller with analog inputs.
Input and output signals of the logic unit are related in such a way that a dominant state on any bus or Tx0 causes a dominant
state on both buses, RINT and Rx0.
The output signal at Rx0 corresponds to the inputs Tx0 and TEXT, independent of the state of the two enable inputs. This is
realized by an internal logical connection.
The pins TEXT and RINT are used for connecting the internal logics of several ICs to obtain versions with more than two bus
outputs. If a dominant bit is received from at least one of the two bus systems (under the condition of feedback suppression) or
from Tx0, RINT carries the low-level. Otherwise RINT is high. A low-level at TEXT activates both transmitters causing a dominant
state on both busses and sets Rx0 to the low-level. A high-level at TEXT does not influence the transceiver.
7.6 Power-on-Reset (POR)
While Vcc voltage is below the POR level, the POR circuit makes sure that:
• The counter is kept in the reset mode and stable state without current consumption
• Inputs are disabled (don't care)
• Outputs are high impedant; only Rx0 = high-level
• Analog blocks are in power down
• Oscillator not running and in power down
• CANHx and CANLx are recessive
• VREF output high impedant for POR not released
AMI Semiconductor – Rev. 1.4, May 05 - Preliminary
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