AMIS-720649 Datasheet, PDF (6/10 Pages) AMI SEMICONDUCTOR – Contact Image Sensor

AMIS-720649: Contact Image Sensor
Data Sheet
6.1 Definitions of Electro-Optical Specifications
All electrical specifications are measured at a pixel rate of 2.0MHz, a temperature of 25^°C, Vdd = 5.0V, and at an integration time of
2.2ms. The average output voltage (Vpavg), is adjusted to approximately 1.0V, unless stated otherwise. The modules’ internal green
LED (525 ± 20nm) was used as the light source for measurements requiring illumination. As a guideline, the recommended load on the
output should be 1KΩ<RL<10kΩ. All measurements were taken with a 2kΩ load on the output.
1. Sensitivity (Sv) is defined as the slope of the Vpavg vs. Exposure curve.
2. Saturation voltage (VSat) is defined as the maximum video output voltage swing measured from the dark level to the saturation level. It is measured by using the
module LED light source with the module imaging a uniform white target. The LED light level is increased until the output voltage no longer increases with an
increase in the LED brightness. The dark level is set by the voltage on VR and in a typical CIS module application, sits at approximately 0.7V.
3. Photo-response non-uniformity (Up): Up = ((Vpmax-Vpavg)/Vpavg) x 100% or ((Vpavg-Vpmin)/Vpavg) x 100%, whichever is the greater, where Vpmax is the
maximum pixel output voltage in the light, Vpmin is the minimum pixel output voltage in the light and Vpavg is average output voltage of all pixels in the light.
4. Adjacent photo-response non-uniformity (Upn): Upn = Max ((Vpn – Vpn+1) / Min (Vpn, Vpn+1)) x 100%, where Vpn is the pixel output voltage of pixel n in the light.
5. Dark output voltage (Vd): Vd is the average dark output level and is essentially the offset level of the video output in the dark. The dark level is set by the voltage
on VR and in a typical CIS module application, sits at approximately 0.7V.
6. Dark output non-uniformity (Ud): Ud = Vdmax-Vdmin, where Vdmax is the maximum pixel output voltage in the dark and Vdmin is the minimum pixel output
voltage in the dark.
7. Random thermal noise (rms), (Vno), is the standard deviation of n pixels in the dark. A sample size n= 64 was used. A 4mV rms value has a peak-peak equivalent
of 24mV.
8. Sensor-to-sensor photo-response non-uniformity (Usensor): Usensor = (Vpavg – Wavg) / Wavg), where Wavg is the average output of all sensors on the same
wafer that pass all other specifications.
9. Photo-response linearity (PRL): Photo-response linearity is defined as the max deviation of response compared to a best fit line. The data points plotted are those
that lie within ten percent of the saturation level and ninety percent of the saturation level. Outside these ranges the module is operating close to non-linearity.
7.0 Recommended Operating Conditions
Table 3 lists the recommended operating conditions @ 25^°C.
Table 3: Recommended Operating Conditions @ 25^°C
Parameter
Symbol
Min. Typ. Max.
Units
Power supply
Clock input voltage high level ⁽¹⁾
Clock input voltage low level ⁽¹⁾
Vdd
4.5
5.0
5.5
V
2.8
Vdd
Vdd
V
0
0
0.8
V
Power supply current
IDD (sensor selected)
IDD (sensor not selected)
3.2
5
mA
2.6
4
mA
Reference voltage ⁽²⁾
VR
0.6
0.7
1.1
V
Clock frequency ⁽³⁾
0.5
2.0
2.5
MHz
Pixel rate
Integration time (line scan rate) ⁽⁴⁾
First die
Subsequent die
Clock pulse duty cycle ⁽⁵⁾
0.5
2.0
2.5
MHz
Tint
150
138
µs
µs / die
75
%
Notes:
1. Applies to all clocks; GBST, SIC, SI, and CLK.
2. The dark level is set by the voltage on the VR input pad, which is internally set to a typical value of 0.7V. Alternatively, if the user wishes to use a dark level greater
than this, then VR can be supplied externally.
3. Although the device will operate with a pixel rate of less than 500kHz, it is recommended that the device be operated above 500kHz to maintain performance
characteristics. Operating below 500kHz may result in a significant integration of dark current.
4. Tint is the integration time of a single sensor and is the time between two start pulses. The minimum integration time is the time it takes to clock out 29 inactive
pixels and 344 active pixels. If several sensors are cascaded together in a module then the minimum integration time is the time it takes to clock out 29 inactive
pixels and 344 active pixels from the first sensor and 344 pixels from each of all subsequent sensors, at a given frequency.
5. The clock duty cycle is defined as the ratio of the positive duration of the clock to its period.
AMI Semiconductor – Dec. 05, M-20488-001
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