AMIS-40615 Datasheet, PDF (4/17 Pages) AMI SEMICONDUCTOR – LIN Transceiver with 3.3V Voltage Regulator

AMIS-40615
LIN Transceiver with 3.3V Voltage Regulator
Data Sheet
6.0 Typical Application
6.1 Application Schematic
The EMC immunity of the master-mode device can be further enhanced by adding a capacitor between the LIN output and ground. The
optimum value of this capacitor is determined by the length and capacitance of the LIN bus, the number and capacitance of slave
devices, the pull-up resistance of all devices (master & slave), and the required time constant of the system, respectively.
V_cc voltage must be properly stabilized by external capacitors: capacitor of min. 80nF (ESR<10mΩ) in parallel with a capacitor of min.
8µF (ESR<1Ω).
VBAT
LIN
WAKE
GND
10 uF 100nF
Master Node
10 uF 100nF
V_BB
INH ₁
11
V_CC
14 RxD
13
TxD
LIN ₂ ^{AMIS- 12}
40615 ₉
EN
WAKE ^{5 7 3}
10
4 11 8
STB
GND
V_CC
Micro
controller
GND
VBAT
LIN
WAKE
GND
10 uF 100nF
Slave Node
10 uF 100nF
V_BB
1
11
V_CC
14 RxD
13
TxD
LIN ₂ ^{AMIS- 12}
40615 ₉
EN
WAKE ^{5 7 3}
10
4 11 8
STB
GND
V_CC
Micro
controller
GND
KL30
LIN-BUS
KL31
Figure 2: Typical Application Diagram
6.2 Pin Description
6.2.1. Pin Out (top view)
V_BB 1
LIN 2
GND ³
GND 4
WAKE ⁵
INH 6
OTP_ZAP ⁷
14 V_CC
13 RxD
12 TxD
11 GND
10 STB
9 _EN
8 _TEST
PC20060426.1
Figure 3: Pin Configuration
AMI Semiconductor – March 2007, M-20544-001
4
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