AMIS-30623 Datasheet, PDF (26/67 Pages) AMI SEMICONDUCTOR – LIN Microstepping Motordriver

AMIS-30623 LIN Microstepping Motordriver
Data Sheet
The <StepLoss> signal is used to block successive motions. Also this signal will be cleared after Vbb > UV1, making updates of
TagPos possible.
The implementation is illustrated in the state diagram below.
HS = f (UV2SIG, OVC1, OVC2, CPFail, …)
If UV2SIG = 1 THEN TagPos ≠ ActPos
ELSE copy TagPos = ActPos
GotoPos
HardStop
Stopped
ShutDown
HS to Positioner
GetStatus
GetFullStatus
PWM disabled
Motor in HiZ
TagPos ≠ ActPos
Vbb > UV1
Figure 18: State Diagram Autarkic Under-voltage Handling
In Stop mode 1 AMIS-30623 is in the Stopped state. Because Vbb < UV2 it enters the ShutDown state. Once Vbb > UV1 the Stopped
state will be entered again.
In Stop mode 2 AMIS-30623 is in the GotoPos state. Because Vbb < UV2 the UV2SIG is set and the HardStop state is entered. After
the hardstop motion is finished (HS to Positioner) it enters the Stopped state. UV2SIG = 1 so the TagPos is not copied in Actpos, and
the shutdown stated is entered. Once Vbb > UV1 the Stopped state will be entered again and because TagPos = Actpos C623 moves
to GotoPos again. <UV2SIG>, <CPFail> and <Steploss> are cleared when Vbb > UV1 so HardStop is not entered again.
15.2.8. OTP register
OTP Memory Structure
The table below shows how the parameters to be stored in the OTP memory are located.
Table 17: OTP Memory Structure
Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
0x00
OSC3
OSC2
OSC1
OSC0
IREF3
0x01 EnableLIN
TSD2
TSD1
TSD0
BG3
0x02
AbsThr3 AbsThr2 AbsThr1 AbsThr0
PA3
0x03
Irun3
Irun2
Irun1
Irun0
Ihold3
0x04
Vmax3
Vmax2
Vmax1
Vmax0
Vmin3
0x05
SecPos10 SecPos9 SecPos8
Shaft
Acc3
0x06
SecPos7 SecPos6 SecPos5 SecPos4 SecPos3
0x07
DelThr3 DelThr2 DelThr1 DelThr0 StepMode1
Bit 2
IREF2
BG2
PA2
Ihold2
Vmin2
Acc2
SecPos2
StepMode0
Bit 1
IREF1
BG1
PA1
Ihold1
Vmin1
Acc1
Failsafe
LOCKBT
Bit 0
IREF0
BG0
PA0
Ihold0
Vmin0
Acc0
SleepEn
LOCKBG
Parameters stored at address 0x00 and 0x01 and bit LOCKBT are already programmed in the OTP memory at circuit delivery. They
correspond to the calibration of the circuit and are just documented here as an indication.
Each OPT bit is at ‘0’ when not zapped. Zapping a bit will set it to ‘1’. Thus only bits having to be at ‘1’ must be zapped. Zapping of a bit
already at ‘1’ is disabled. Each OTP byte will be programmed separately (see command SetOTPparam). Once OTP programming is
completed, bit LOCKBG can be zapped, to disable future zapping, otherwise any OTP bit at ‘0’ could still be zapped by using a
SetOTPparam command.
AMI Semiconductor – June 2006, Rev 3.0
26
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