AMIS-721250 Datasheet, PDF (2/12 Pages) AMI SEMICONDUCTOR – Contact Image Sensor

AMIS-721250: Contact Image Sensor
Data Sheet
3.0 Unique Features
There are six unique features incorporated into the AMIS-721250 which improve the sensor’s performance.
3.1 Pixel-to-Pixel Offset Cancellation Circuit
The sensor employs a pixel-to-pixel offset cancellation circuit, which reduces the fix pattern noise (FPN), and amplifier offsets. In
addition, this innovative circuit design greatly improves the optical linearity and low noise sensitivity.
3.2 Parallel Integrate, Transfer and Hold
The sensor has a parallel integrate, transfer and hold feature, which allows the sensor to be read out while photon integration is taking
place. These features are approached through the use of an integrate-and-hold cell, located at each pixel site. Each pixel’s charge is
read from its storage site as the sensor’s shift register sequentially transfers each pixel’s charge onto a common video line.
3.3 Dual Scan Initiation Inputs, GBST and SI
Each sensor has two scan initiation inputs, the global start pulse (GBST) and the start pulse (SI), which are compatible with standard
3.3V CMOS clocks. These clocks help to reduce the sensor-to-sensor transition FPN by initializing and preprocessing all sensors
simultaneously before they start their readout scan. The internal shift register starts the scan after GBST is clocked in on the falling
edge of the clock input (CLK).
The start input control (SIC) selects the first sensor in a sequence of cascaded sensors to operate with 55 clock cycles of delay by
connecting it to Vdd and to ground for all subsequent sensors. Then, only the first sensor clocks out 110 inactive pixels (55 clocks
cycles) before accessing its first active pixel. During these 55 clock cycles, the first sensor and all of the subsequent cascaded sensors
cycle through their pre-scan initialization process. After initialization, only the first sensor starts its read cycle with its first-active pixel
appearing on the 56^th clock cycle. The second and subsequent sensors await the entry of their SI. Furthermore, the first sensor’s SI is
left unconnected, while the subsequent sensors all have their SI’s connected to the SO of their respective preceding sensor. The
external scan SI is connected to all of the sensors' GBST inputs.
For example in the 1200dpi mode, when the first sensor completes its scan, its end-of-scan (SO) appears on the falling edge of 389^th
clock cycle after the entry of GBST and 20 pixels before its last pixel, in order to have a continuous pixel readout between sensors in a
module. This SO enters as the SI clock of the second and subsequent sensors; hence all subsequent sensors will start their register
scan after each of the preceding sensors completes its scan.
3.4 Power Saving
Each sensor incorporates a power-saving feature such that each chips amplifier is only turned on when its pixels are ready to be read
out.
3.5 Common Reference Voltage between Cascaded Sensors
Each sensor has an input/output bias control (VREF), which serves as an offset voltage reference. Each bias control pad is connected
to an internal bias source and tied to its own amplifier’s reference bias input. In operation, these pads on every sensor are connected
together. Each sensor then “shares” the same bias level to maintain a constant bias among all of the sensors.
3.6 Selectable Resolutions of 600dpi or 1200dpi
The switch control input (SC) is connected to ground or to Vdd to set the sensor to operate in the 600dpi or 1200dpi mode, respectively.
In the 1200dpi mode, all 688 pixels are clocked out, whereas in the 600dpi mode, pixels one and two are combined, three and four are
combined and so on up to pixels 687 and 688 being combined. One half of the pixel amplifiers and one half of the scanning register are
then disabled. As a result, sensitivity in the 600dpi mode will be twice that of the 1200dpi mode. The 600dpi readout time will be
approximately half of the 1200dpi readout time. Unlike a CCD array, both the 600dpi and 1200dpi arrays can operate with the same
clock frequency.
AMI Semiconductor – Dec. 05, M-20496-004
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