AMIS-30521 Datasheet, PDF (19/26 Pages) AMI SEMICONDUCTOR – Micro-stepping Motor Driver

AMIS-30521 Micro-stepping Motor Driver
Data Sheet
9.3 SPI Control Registers
All SPI control registers have Read/Write access and default to "0" after power-on or hard reset.
Table 13: SPI Control Register 0
Control Register 0 (CR0)
Address _Content
Bit 7
Bit 6
Access
R/W R/W
01h
Reset
0
0
Data
SM[2:0]
Bit 5
R/W
0
Structure
Bit 4
Bit 3
R/W R/W
0
0
CUR[4:0]
Bit 2
R/W
0
Bit 1
R/W
0
Bit 0
R/W
0
Where:
R/W
Reset:
SM[2:0]:
CUR[4:0]:
Read and Write access
Status after power-On or hard reset
Step mode
Current amplitude
Table 14: SPI Control Register 1
Address
02h
Content
Access
Reset
Data
Bit 7
R/W
0
DIRCTRL
Control Register 1 (CR1)
Structure
Bit 6 Bit 5 Bit 4 Bit 3
R/W R/W R/W R/W
0
0
0
0
NXTP -
- PWMF
Bit 2
R/W
0
PWMJ
Bit 1
Bit 0
R/W R/W
0
0
EMC[1:0]
Where:
R/W
Reset::
DIRCTRL
NXTP
PWMF
PWMJ
EMC[1:0]
Read and Write access
Status after power-on or hard reset
Direction control
NEXT polarity
PWM frequency
PWM jitter
EMC slope control
Table 15: SPI Control Register 2
Address
03h
Content
Access
Reset
Data
Bit 7
R/W
0
MOTEN
Control Register 2 (CR2)
Structure
Bit 6 Bit 5 Bit 4 Bit 3
R/W R/W R/W R/W
0
0
0
0
SLP SLAG SLAT -
Bit 2
R/W
0
-
Bit 1
R/W
0
-
Bit 0
R/W
0
-
Where:
R/W
Reset:
MOTEN
SLP
SLAG
SLAT
Read and Write access
Status after power-On or hard reset
Motor enable
Sleep
Speed load angle gain
Speed load angle transparency
Table 16: SPI Control Parameter Overview SLAT
Symbol
Description
SLAT
Speed Load Angle Transparency bit
Status
<SLAT> = 0
<SLAT> = 1
Behavior
SLA is transparent
SLA is NOT transparent
AMI Semiconductor – June 2007, M-20683-001
19
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