AM8530H Datasheet, PDF (60/194 Pages) Advanced Micro Devices – Serial Communications Controller

AMD
Data Communication Modes Functional Description
D1 D0 P D4 D3 D2 D1 D0
Figure 4–6. Five Bits/Character with Parity
The character length may be changed at any time before the new number of bits have
been assembled by the receiver. Care should be exercised, however, as unexpected re-
sults may occur if not properly timed. A representative example of switching from five bits
to eight bits and back to five bits is shown in Figure 4–7.
Time
RECEIVE DATA BUFFER
8 7 6 5 4 3 2 1 5 BITS
Change From Five to Eight
13 12 11 10 9 8 7 6 8 BITS
21 20 19 18 17 16 15 14 8 BITS
Change From Eight to Five
29 28 27 26 25 24 23 22 5 BITS
34 33 32 31 30 29 28 27 5 BITS
39 38 37 36 35 34 32 31
Figure 4–7. Changing Character Length
4.4.2 Rx Parity
In all modes of operation bit D0 (Parity Enable) of WR4 determines whether a Parity
check is done. If this bit is set to ‘1’, the receiver calculates a parity check on every char-
acter received, as selected by bit D1 (Parity Even/Odd) of WR4, and compares it with
parity check bit transmitted. If a discrepancy is found the Parity Error status bit in the Re-
ceive Error FIFO is set at the same time that the character is transferred to the Receive
Data FIFO; otherwise, the character received will be assumed to be error free.
The additional bit per character will be visible in the Receive Data FIFO if the data plus
parity is eight bits or less. The parity bit will not be visible when there are eight data bits
per character.
4–8