AM8530H Datasheet, PDF (177/194 Pages) Advanced Micro Devices – Serial Communications Controller

AMD
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SCC Application Notes
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Figure 7–17. Slew Rate Controlled Outputs
Common-Mode Problem
The common-mode voltage problem can be resolved by using transformer isolation at the
transceiver-cable interface. The Am7960 provides a high impedance interface to the cou-
pling transformer. It also implements a user-transparent Manchester encoding/decoding
scheme that limits the frequency of output data signals to within a narrow range.
Noise Immunity
In the receiver section of the Am7960 a signal qualifier minimizes false starts, thus im-
proving reliability. Line activity is detected when the input signal crosses the threshold.
The receive clock is acquired when there are two transitions of the input signal during a
bit time interval.
Digital Sampling
The internal DPLL runs at 16 times the data rate. Hence, each bit of the received signal is
quantized into 16 samples. The DPLL is free-running when the line is quiet but synchro-
nizes within 1/16 of a bit on the first valid signal edge. It then opens up a series of win-
dows at the 5/16 to 7/16, 12, and 9/16 to 11/16 positions of the expected bit cell.
Zero-crossings within these windows set a Shorten, Center, or Lengthen flag that makes
the loop adjust for sampling of the next bit cell. The internal circuitry samples the incom-
ing data at 1/4 and 3/4 bit intervals. A transition of voltage levels between these two time
slots indicates the arrival of a valid Manchester data bit.
7.6.3 Hardware Considerations
The Am7960 can be used with a Am8530H Serial Communications Controller (SCC) to
build a simple and cost-effective 1 Mb/s data link for office and industrial applications.
The Am8530H is a two channel, software-programmable, device which can adapt to most
system architectures including:
s Bus architectures (full-duplex and half-duplex)
s Token Passing Ring (SDLC Loop Mode)
s STAR Configurations (similar to SLAN)
The power and flexibility of the Am8530H, along with the Am7960’s CSMA-CA access
scheme. Manchester coding of data and output slew rate control enable the system de-
signer to deliver an inexpensive 1 Mb/s LAN.
The straightforward nature of the hardware connections is shown in Figure 7–18. The
Request to Send (RTS) output from the SCC is ORed with inverted Advance Carrier De-
tect (ACD) output to implement the collision avoidance scheme.
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