AM8530H Datasheet, PDF (157/194 Pages) Advanced Micro Devices – Serial Communications Controller

AMD
SCC Application Notes
7.2.2 SCC Interface
Figure 7–2 shows the SCC to CPU interface required for this application. The 8-bit data
bus and control lines all come from the user’s CPU. The Am8530 control lines are RD,
WR, A/B, D/C and CE. PCLK comes from the system clock, or an external crystal, up to
the maximum rate of the SCC. The IEI and the INTACK pins should be pulled up. The
baud-rate generator clock is connected to the RTxC pin.
7.2.3 SCC Initialization
Initialization of the SCC for polled asynchronous communication is divided into two parts;
part one programs the operating modes of the SCC and part two enables them (refer to
Table 7–4). Care must be taken when writing the software to meet the SCC’s Cycle and
Reset Recovery times. The Cycle Recovery time, 6 PCLK cycles, applies to the period
between any Read or Write cycles affecting the SCC. The Reset Recovery time is the
period after a hardware reset caused either by hardware or software; this recovery time
extends the Cycle Recovery time to 11 PCLK cycles.
System
Data
8 D0 – D7
VCC VCC
SCC
IEI
INTACK
Control
5
PCLK
Pin 12 For Channel A
Pin 28 For Channel B
RTxC
XTAL
OSC
2.4576 MHz
OSC
Figure 7–2. SCC Interface
7–8