AM29DL400B_05 Datasheet, PDF (23/47 Pages) Advanced Micro Devices – 4 Megabit (512 K x 8-Bit/256 K x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory

START
Read DQ7–DQ0
Read DQ7–DQ0
Toggle Bit
No
= Toggle?
Yes
No
DQ5 = 1?
Yes
Read DQ7–DQ0
Twice
Toggle Bit
No
= Toggle?
Yes
Program/Erase
Operation Not
Complete, Write
Reset Command
Program/Erase
Operation Complete
Note: The system should recheck the toggle bit even if DQ5
= “1” because the toggle bit may stop toggling as DQ5
changes to “1.” See the subsections on DQ6 and DQ2 for
more information.
Figure 6. Toggle Bit Algorithm
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time
has exceeded a specified internal pulse count limit.
Under these conditions DQ5 produces a “1,” indicat-
ing that the program or erase cycle was not
successfully completed.
The device may output a “1” on DQ5 if the system
tries to program a “1” to a location that was previ-
ously programmed to “0.” Only an erase operation
can change a “0” back to a “1.” Under this condi-
tion, the device halts the operation, and when the
timing limit has been exceeded, DQ5 produces a “1”.
Under both these conditions, the system must write
the reset command to return to reading array data
(or to the erase-suspend-read mode if a bank was
previously in the erase-suspend-program mode).
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the
system may read DQ3 to determine whether or not
erasure has begun. (The sector erase timer does not
apply to the chip erase command.) If additional sec-
tors are selected for erasure, the entire time-out also
applies after each additional sector erase command.
When the time-out period is complete, DQ3 switches
from a “0” to a “1”. If the system can guarantee the
time between additional sector erase commands to
be less than 50 µs, it need not monitor DQ3. See
also the Sector Erase Command Sequence section.
After the sector erase command is written, the sys-
tem should read the status of DQ7 (Data# Polling) or
DQ6 (Toggle Bit I) to ensure that the device has ac-
cepted the command sequence, and then read DQ3.
If DQ3 is “1”, the Embedded Erase algorithm has be-
gun; all further commands (except Erase Suspend)
are ignored until the erase operation is complete. If
DQ3 is “0”, the device will accept additional sector
erase commands. To ensure the command has been
accepted, the system software should check the sta-
tus of DQ3 prior to and following each subsequent
sector erase command. If DQ3 is high on the second
status check, the last command might not have been
accepted.
Table 6 shows the status of DQ3 relative to the other
status bits.
Am29DL400B
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