440SP Datasheet, PDF (82/85 Pages) Applied Micro Circuits Corporation – PowerPC 440SP Embedded Processor

PowerPC 440SP Embedded Processor
Revision 1.23 - Sept 26, 2006
Data Sheet
The following figure shows the timing relationship between SDRAM DDR Data at the input pin and the store of the
data in stage 1.
Figure 11. DDR SDRAM Read Cycle Timing Example
Oversampling Guard Band
DDR 1X Clock
DDR 2X Clock
Memclk (Diff.)
DQS at
MemCntl pin
Data at pin
FeedBack
output
Delayed DQS
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9
Store 1st Data in Stage 2
1X DDR Clk cycle
T1
T2
T3
T4
Data out Stage 1 (0)
Data out Stage 1 (1)
Data out Stage 1 (2)
High
Data out Stage 2
Low
Valid
D0
D2
D1
D3
PLB 1X Clock
82
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