440SP Datasheet, PDF (5/85 Pages) Applied Micro Circuits Corporation – PowerPC 440SP Embedded Processor

Revision 1.23 - Sept 26, 2006
Data Sheet
PPC440SP Functional Block Diagram
PowerPC 440SP Embedded Processor
Figure 2. PPC440SP Functional Block Diagram
Universal
Interrupt
Controller
Clock,
Control,
Reset
Power
Mgmt
Timers
MMU
PPC440
Processor Core
JTAG
32 KB
D-Cache
Trace
32 KB
I-Cache
L2 Cache/SRAM
DCRs
DCR Bus
GPT
GPIO
IIC1
IIC0
UART2
UART1
UART0
On-chip Peripheral Bus (OPB)
OPB
Bridge
Processor Local Bus (PLB)
Low Latency (LL) Segment
High Bandwidth (HB) Segment
MAL
I2O/DMA
Controller
(DMA0 and
DMA1)
Memory
Queue
DDR2 SDRAM
Controller
XOR/DMA
Accelerator
Unit
(DMA2)
DDR PCI-X
PCI0 PCI1 PCI2
Host Local Local
64 bits 64 bits 32 bits
PLB
Arbiter
Ethernet
10/100/
1000
(EMAC)
External
Bus Controller
(EBC)
MII,
GMII
The PPC440SP is a System on a chip, which uses IBM^® CoreConnect Bus™ Architecture.
Implemented with the Crossbar option, the IBM CoreConnect buses provide:
• 128-bit Data, 64-bit Address PLB interfaces up to 166.66MHz, 2.6GB/s on both the Read and Write data
paths (10.6GB/sec total)
• 32-bit OPB interfaces up to 83.33MHz, 333MB/s
Address Maps
The PPC440SP incorporates two address maps. The first is a fixed processor system memory address map. This
address map defines the possible contents of various processor accessible address regions. The second address
map identifies the system Device Configuration Registers (DCRs). DCRs are accessed by software running on the
PPC440SP processor through the use of mtdcr and mfdcr instructions.
AMCC Proprietary
5