ES1010SI Datasheet, PDF (9/11 Pages) Altera Corporation – 12V Hot-Swap Power Distribution Controllers

Page 9
Typical Performance Curves (Continued)
ILOAD
GATE
CLTIM
VOUT
ILOAD
CLTIM
GATE
VOUT
FIGURE 12. IOC REGULATION and TURN-OFF
FIGURE 13. WOC TURN-OFF and RESTART
EVB-ES1010SI Board
The EVB-ES1010SI is default provided as a +12V high side switch controller with the CR level set at ~2.5A. See Figure 11 for
EVB-ES1010SI schematic and Table 3 for BOM. Bias and load connection points are provided along with test points for each IC
pin.
With J1 installed the ES1010SI will be biased from the +12V supply (V_IN) being switched. Connect the load to VLOAD+. EN pin
pulls high internally enabling the ES1010SI if not driven low via EN test point or J2.
With R₃ = 1.24k the CR Vth is set to 24.8mV and with the 10m sense resistor (R₁) the EVB-ES1010SI has a nominal CR level
of 2.5~A. The 0.01µF delay time to latch-off capacitor results in a nominal 1ms before latch-off of output after an OC event.
Reconfiguring the EVB-ES1010SI board for a higher CR level can be done by changing the R_SENSE and/or R_ISET- resistor values as
the provided FET is rated for a much higher current.
VLOAD+
AGND
VOUT
R3
R1
Q1
R2
C1
V_IN
1
8
2 _ES1010SI 7
3
U1
6
4
5
C2
J2
EN
POK
C_CLTIM
C3
R4
J1
+12V
V_BIAS
V_BIAS
FIGURE 14. EVB-ES1010SI HIGH SIDE SWITCH APPLICATION
March 2014 Altera Corporation
09617
March 14, 2014
ES1010SI 12V Hot-Swap Power Distribution Controllers
Rev A