ES1010SI Datasheet, PDF (2/11 Pages) Altera Corporation – 12V Hot-Swap Power Distribution Controllers

Page 2
Ordering Information
PART NUMBER
(Notes 1, 3)
PART
MARKING
TEMPERATURE
RANGE (°C)
PACKAGE
(Pb-free)
PKG.
DWG. #
ES1010SI
1010
-40 to +85
8 Ld SOIC
M8.15
EVB-ES1010SI
Evaluation Platform
NOTES:
1. These Altera Enpirion Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and
100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering
operations). Altera Enpirion Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free
requirements of IPC/JEDEC J STD-020..
Pin Configuration
Pin Descriptions
PIN
NO. SYMBOL
FUNCTION
1
ISET- Current Set
2
ISEN+ Current Sense
3
GATE External FET Gate Drive
Pin
4
GND Chip Return
5
VIN Chip Supply
6
CLTIM Current Limit Timing
Capacitor
7
POK Power Good Indicator
8
EN
Power-ON
ES1010SI
(8 LD SOIC)
TOP VIEW
ISET- 1
ISEN+ 2
GATE 3
GND 4
8 EN
7 POK
6 CLTIM
5 VIN
DESCRIPTION
Connect to the low side of the current sense resistor through the current limiting set resistor. This
pin functions as the current limit programming pin.
Connect to the more positive end of sense resistor to measure the voltage drop across this resistor.
Connect to the gate of the external N-Channel MOSFET. A capacitor from this node to ground
sets the turn-on ramp. At turn-on this capacitor will be charged to V_IN +6.5V by an 14µA
current source.
12V chip supply. This can be either connected directly to the +12V rail supplying the switched
load voltage or to a dedicated GND +12V supply.
Connect a capacitor from this pin to ground. This capacitor determines the time delay between
an overcurrent event and chip output shutdown (current limit time-out). The duration of
current limit time-out is equal to 93k x CLTIM.
Indicates that the voltage on the ISEN+ pin is satisfactory. POK is driven by an open drain
N-Channel MOSFET and is pulled low when the output voltage (VISEN+) is less than the UV
level for the particular IC.
EN is used to control and reset the chip. The chip is enabled when EN pin is driven high to a
maximum of 5V or is left open. Do not drive this input >5V. After a current limit time-out, the
chip is reset by a low level signal applied to this pin. This input has 20µA pull-up capability.
ES1010SI 12V Hot-Swap Power Distribution Controllers
09617
March 14, 2014
March 2014 Altera Corporation
Rev A