5SGXEB6R2F40C3N Datasheet, PDF (49/70 Pages) Altera Corporation – Stratix V Device Handbook

Chapter 2: DC and Switching Characteristics for Stratix V Devices
Switching Characteristics
2–21
Table 2–23 shows the V_OD settings for the GT channel.
Table 2–23. Typical V_OD Setting for GT Channel, TX Termination = 100 —Preliminary
Symbol
V_OD Setting
0
V_OD Value (mV)
0
1
200
V_OD differential peak to peak typical
2
400
3
600
4
800
5
1000
Core Performance Specifications
This section describes the clock tree, phase-locked loop (PLL), digital signal
processing (DSP), memory blocks, configuration, and JTAG specifications.
Clock Tree Specifications
Table 2–24 lists the clock tree specifications for Stratix V devices.
Table 2–24. Clock Tree Performance for Stratix V Devices—Preliminary ⁽¹⁾
Symbol
Performance
Unit
–2 Speed Grade
–3 Speed Grade
–4 Speed Grade
Global and
Regional Clock
717
700
500
MHz
Periphery Clock
550
500
500
MHz
Note to Table 2–24:
(1) The Stratix V ES devices are limited for the 600 MHz core clock network frequency.
PLL Specifications
Table 2–25 lists the Stratix V PLL specifications when operating in both the
commercial junction temperature range (0° to 85°C) and the industrial junction
temperature range (–40° to 100°C).
Table 2–25. PLL Specifications for Stratix V Devices—Preliminary ⁽¹⁾ (Part 1 of 3)
Symbol
f_IN
f_INPFD
f_FINPFD
f_VCO
t_EINDUTY
Parameter
Input clock frequency (–2 speed grade)
Input clock frequency (–3 speed grade)
Input clock frequency (–4 speed grade)
Input frequency to the PFD
Fractional Input clock frequency to the PFD
PLL VCO operating range (–2 speed grade)
PLL VCO operating range (–3 speed grade)
PLL VCO operating range (–4 speed grade)
Input clock or external feedback clock input duty cycle
Min
Typ
Max
Unit
5
—
800 ⁽²⁾
MHz
5
—
700 ⁽²⁾
MHz
5
—
650 ⁽²⁾
MHz
5
—
325
MHz
50
—
133
MHz
600
—
1600
MHz
600
—
1400
MHz
600
—
1300
MHz
40
—
60
%
February 2012 Altera Corporation
Stratix V Device Handbook
Volume 1: Overview and Datasheet