5SGXEB6R2F40C3N Datasheet, PDF (24/70 Pages) Altera Corporation – Stratix V Device Handbook

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Chapter 1: Stratix V Device Family Overview
Automatic Single Event Upset Error Detection and Correction
Partial reconfiguration is supported in the following configurations:
■ Partial reconfiguration through the FPP x16 I/O interface
■ CvP
■ Soft internal core, such as the Nios^® II processor.
Automatic Single Event Upset Error Detection and Correction
Stratix V devices offer single event upset (SEU) error detection and correction
circuitry that is robust and easy to use. The correction circuitry includes protection for
configuration RAM (CRAM) programming bits and user memories. The CRAM is
protected by a continuously running cyclical redundancy check (CRC) error detection
circuit with integrated ECC that automatically corrects one or double-adjacent bit
errors and detects higher order multi-bit errors. When more than two errors occur,
correction is available through a core programming file reload that refreshes a design
while the FPGA is operating.
The physical layout of the FPGA is optimized to make the majority of multi-bit upsets
appear as independent single- or double-adjacent bit errors, which are automatically
corrected by the integrated CRAM ECC circuitry. In addition to the CRAM protection
in Stratix V devices, user memories include integrated ECC circuitry and are
layout-optimized to enable error detection of 3-bit errors and correction for 2-bit
errors.
HardCopy V Devices
HardCopy V ASICs offer the lowest risk and lowest total cost in ASIC designs with
embedded high-speed transceivers. You can prototype and debug with Stratix V
FPGAs, then use HardCopy V ASICs for volume production. The proven turnkey
process creates a functionally equivalent HardCopy V ASIC with or without
embedded transceivers to meet all timing constraints in as little as 12 weeks.
The powerful combination of Stratix V FPGAs and HardCopy V ASICs can help you
meet your design requirements. Whether you plan for ASIC production and require
the lowest-risk, lowest-cost path from specification to production or require a cost
reduction path for your FPGA-based systems, Altera provides the optimal solution
for power, performance, and device bandwidth.
Stratix V Device Handbook
Volume 1: Overview and Datasheet
February 2012 Altera Corporation