5SGXEB6R2F40C3N Datasheet, PDF (13/70 Pages) Altera Corporation – Stratix V Device Handbook

Chapter 1: Stratix V Device Family Overview
1–7
Stratix V Family Plan
Table 1–3 lists the Stratix V GS device features.
Table 1–3. Stratix V GS Device Features
Features
Logic Elements (K)
Registers (K)
14.1-Gbps transceivers
PCIe hard IP blocks
Fractional PLLs
M20K Memory Blocks
M20K Memory (MBits)
Variable Precision Multipliers (18x18)
Variable Precision Multipliers (27x27)
DDR3 SDRAM x72 DIMM Interfaces
5SGSD3
236
356
12 or 24
1
20
688
13
1,200
600
2
5SGSD4
360
543
12, 24, or 36
1
20 ⁽¹⁾
957
19
2,088
1,044
4
5SGSD5
457
690
24 or 36
1
24
2,014
39
3,180
1,590
4
5SGSD6
583
880
36 or 48
1, 2, or 4
28
2,320
45
3,550
1,775
6
5SGSD8
695
1,050
36 or 48
1, 2, or 4
28
2,567
50
3,926
1,963
6
User I/Os, Full-Duplex LVDS, 14.1-Gbps Transceivers
Package ^{(2), (3), (4), (5)}
EH29-H780
HF35-F1152 ⁽⁶⁾
KF40-F1517 ⁽⁶⁾
NF45-F1932 ⁽⁶⁾
5SGSD3
360, 90, 12^H
432, 108, 24
—
—
5SGSD4
360, 90, 12^H
432, 108, 24
696, 174, 36
—
5SGSD5
—
552, 138, 24
696, 174, 36
—
5SGSD6
—
—
696, 174, 36
840, 210, 48
5SGSD8
—
—
696, 174, 36
840, 210, 48
Notes to Table 1–3:
(1) The F1517 package contains 24 PLLs. The other packages with this device contain 20 PLLs.
(2) Packages are flipchip ball grid array (1.0-mm pitch).
(3) LVDS counts are full duplex channels. Each full duplex channel is one TX pair plus one RX pair.
(4) Each package row offers pin migration (common circuit board footprint) for all devices in the row.
(5) ^H indicates that this device is only available in a hybrid package. Hybrid packages are slightly larger than conventional FBGAs. Refer to Altera’s
packaging documentation for more information.
(6) Migration between select Stratix V GS devices and Stratix V GX devices is available. For more information, refer to Table 1–5 on page 1–9.
February 2012 Altera Corporation
Stratix V Device Handbook
Volume 1: Overview and Datasheet