5CEBA5F23C7N Datasheet, PDF (47/58 Pages) Altera Corporation – Cyclone V Device Datasheet

Configuration Specification
Page 47
AS Configuration Timing
Figure 19 shows the timing waveform for the active serial (AS) x1 mode and AS x4
mode configuration timing.
Figure 19. AS Configuration Timing Waveform for Cyclone V Devices
nCONFIG
t_CF2ST1
nSTATUS
CONF_DONE
nCSO
DCLK
AS_DATA0/ASDO
AS_DATA1 (1)
INIT_DONE (3)
t_CO
Read Address
t_DH
t_SU
bit 0
bit 1
bit (n − 2) bit (n − 1)
t_CD2UM (2)
User I/O
User Mode
Notes to Figure 19:
(1) If you are using AS x4 mode, this signal represents the AS_DATA[3..0] and EPCQ sends in 4-bits of data for each DCLK cycle.
(2) The initialization clock can be from the internal oscillator or the CLKUSR pin.
(3) After the option bit to enable the INIT_DONE pin is configured into the device, INIT_DONE goes low.
Table 51 lists the timing parameters for AS x1 and AS x4 configurations in Cyclone V
devices.
The minimum and maximum numbers apply to both the internal oscillator and
CLKUSR when either one is used as the clock source for device configuration.
The t_CF2CD, t_CF2ST0, t_CFG, t_STATUS, and t_CF2ST1 timing parameters are identical to the
timing parameters for passive serial (PS) mode listed in Table 53 on page 1–49. You
can obtain the t_CF2ST1 value if you do not delay configuration by externally holding
nSTATUS low.
Table 51. AS Timing Parameters for AS x1 and x4 Configurations in Cyclone V Devices—Preliminary
Symbol
t_CO
t_SU
t_DH
t_CD2UM
t_CD2CU
t_CD2UMC
Parameter
DCLK falling edge to the AS_DATA0/ASDO output
Data setup time before the falling edge on DCLK
Data hold time after the falling edge on DCLK
CONF_DONE high to user mode
CONF_DONE high to CLKUSR enabled
CONF_DONE high to user mode with CLKUSR option on
Minimum
Maximum Unit
—
4
µs
1.5
—
ns
0
—
ns
175
437
µs
4 x maximum DCLK period
—
—
t_CD2CU + (T_init x CLKUSR
—
—
period)
T_init
Number of clock cycles required for device initialization
17,408
—
Cycles
June 2013 Altera Corporation
Cyclone V Device Datasheet