5CEBA5F23C7N Datasheet, PDF (40/58 Pages) Altera Corporation – Cyclone V Device Datasheet

Page 40
Switching Characteristics
Figure 16 shows the timing diagram for NAND data read timing characteristics.
Figure 16. NAND Data Read Timing Diagram
NAND_CE
NAND_RE
NAND_DQ[7:0]
NAND_RB
T_cea
T_rp
T_reh
T
rhz
T_rea
Dout
T_rb
ARM Trace Timing Characteristics
Table 44 lists the ARM trace timing characteristics for Cyclone V devices.
Table 44. ARM Trace Timing Requirements for Cyclone V Devices—Preliminary
Description
CLK clock period
CLK maximum duty cycle
CLK to D0 –D7 output data delay
Min
Typ
Max
Unit
TBD
8
TBD
ns
TBD
—
TBD
%
–1
—
1
ns
UART Interface
The maximum UART baud rate is 6.25 megasymbols per second.
GPIO Interface
Table 45 lists the general-purpose I/O (GPIO) pulse width for Cyclone V devices.
Table 45. GPIO Pulse Width for Cyclone V Devices—Preliminary
Description
Minimum detectable pulse width
Min
Max
Unit
40
TBD
ns
CAN Interface
The maximum controller area network (CAN) data rate is 1 Mbps.
Cyclone V Device Datasheet
June 2013 Altera Corporation