EPM7128SQC160-10 Datasheet, PDF (44/66 Pages) Altera Corporation – Programmable Logic Device Family

MAX 7000 Programmable Logic Device Family Data Sheet
Tables 31 and 32 show the EPM7128S AC operating conditions.
Table 31. EPM7128S External Timing Parameters Note (1)
Symbol
Parameter
Conditions
Speed Grade
Unit
-6
-7
-10
-15
Min Max Min Max Min Max Min Max
t_PD1
t_PD2
t_SU
t_H
t_FSU
t_FH
t_CO1
t_CH
t_CL
t_ASU
t_AH
t_ACO1
t_ACH
t_ACL
t_CPPW
t_ODH
t_CNT
f_CNT
t_ACNT
f_ACNT
f_MAX
Input to non-registered output C1 = 35 pF
6.0
7.5
10.0
15.0 ns
I/O input to non-registered
output
C1 = 35 pF
6.0
7.5
10.0
15.0 ns
Global clock setup time
3.4
6.0
7.0
11.0
ns
Global clock hold time
0.0
0.0
0.0
0.0
ns
Global clock setup time of fast
input
2.5
3.0
3.0
3.0
ns
Global clock hold time of fast
input
0.0
0.5
0.5
0.0
ns
Global clock to output delay C1 = 35 pF
4.0
4.5
5.0
8.0 ns
Global clock high time
3.0
3.0
4.0
5.0
ns
Global clock low time
3.0
3.0
4.0
5.0
ns
Array clock setup time
0.9
3.0
2.0
4.0
ns
Array clock hold time
1.8
2.0
5.0
4.0
ns
Array clock to output delay
C1 = 35 pF
6.5
7.5
10.0
15.0 ns
Array clock high time
3.0
3.0
4.0
6.0
ns
Array clock low time
3.0
3.0
4.0
6.0
ns
Minimum pulse width for clear (2)
and preset
3.0
3.0
4.0
6.0
ns
Output data hold time after
C1 = 35 pF (3) 1.0
1.0
1.0
1.0
ns
clock
Minimum global clock period
6.8
8.0
10.0
13.0 ns
Maximum internal global clock (4)
frequency
147.1
125.0
100.0
76.9
MHz
Minimum array clock period
6.8
8.0
10.0
13.0 ns
Maximum internal array clock (4)
frequency
147.1
125.0
100.0
76.9
MHz
Maximum clock frequency
(5)
166.7
166.7
125.0
100.0
MHz
44
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