EPM7128SQC160-10 Datasheet, PDF (18/66 Pages) Altera Corporation – Programmable Logic Device Family

MAX 7000 Programmable Logic Device Family Data Sheet
Programming Times
The time required to implement each of the six programming stages can
be broken into the following two elements:
■ A pulse time to erase, program, or read the EEPROM cells.
■ A shifting time based on the test clock (TCK) frequency and the
number of TCK cycles to shift instructions, address, and data into the
device.
By combining the pulse and shift times for each of the programming
stages, the program or verify time can be derived as a function of the TCK
frequency, the number of devices, and specific target device(s). Because
different ISP-capable devices have a different number of EEPROM cells,
both the total fixed and total variable times are unique for a single device.
Programming a Single MAX 7000S Device
The time required to program a single MAX 7000S device in-system can
be calculated from the following formula:
tPROG
=
tPPULSE
+
-^C----^y---^c---^l--^e---^P----^T----^C-----^K--
fTCK
where: t_PROG
t_PPULSE
Cycle_PTCK
f_TCK
= Programming time
= Sum of the fixed times to erase, program, and
verify the EEPROM cells
= Number of TCK cycles to program a device
= TCK frequency
The ISP times for a stand-alone verification of a single MAX 7000S device
can be calculated from the following formula:
tVER
=
tVPULSE
+
C_-----y_---c_---l_--e_{---V-----T----C----K---}
fTCK
where: t_VER
= Verify time
t_VPULSE = Sum of the fixed times to verify the EEPROM cells
Cycle_VTCK = Number of TCK cycles to verify a device
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Altera Corporation