EP1S30F780C6 Datasheet, PDF (422/864 Pages) Altera Corporation – Stratix Device Handbook, Volume 1

DDR Memory Support Overview
Figure 3–14. DQ Captures with Non-Inverted & Inverted Shifted DQS
DQ & DQS Signals
DQ at the pin
D_{n − 1}
D_n
DQS at the pin
Shifted DQS Signal is Not Inverted
DQS shifted
by 90˚
Output of register A₁
(dataout_h)
Output of register B₁
Output of latch C₁
(dataout_l)
Shifted DQS Signal is Inverted
DQS inverted and
shifted by 90˚
Output of register A₁
(dataout_h)
Output of register B₁
Output of latch C₁
(dataout_l)
D_{n − 1}
D_{n − 2}
D_n
D_{n − 2}
D_{n − 2}
D_{n − 1}
D_{n − 3}
D_n
D_{n − 1}
3–26
Stratix Device Handbook, Volume 2
Altera Corporation
June 2006