EP1S30F780C6 Datasheet, PDF (260/864 Pages) Altera Corporation – Stratix Device Handbook, Volume 1

Timing Model
Table 4–118. Stratix Maximum Input Clock Rate for CLK[0, 2, 9, 11] Pins &
FPLL[10..7]CLK Pins in Wire-Bond Packages (Part 2 of 2)
I/O Standard
LVCMOS
GTL+
SSTL-3 Class I
SSTL-3 Class II
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
1.5-V HSTL Class I
1.8-V HSTL Class I
CTT
Differential 1.5-V HSTL
C1
LVPECL (1)
PCML (1)
LVDS (1)
HyperTransport
technology (1)
-6 Speed -7 Speed -8 Speed
Grade Grade Grade
422
390
390
250
200
200
350
300
300
350
300
300
350
300
300
350
300
300
350
300
300
350
300
300
350
300
300
350
300
300
250
200
200
350
300
300
717
640
640
375
350
350
717
640
640
717
640
640
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Table 4–119. Stratix Maximum Input Clock Rate for CLK[1, 3, 8, 10] Pins in
Wire-Bond Packages (Part 1 of 2)
I/O Standard
LVTTL
2.5 V
1.8 V
1.5 V
LVCMOS
GTL+
SSTL-3 Class I
SSTL-3 Class II
SSTL-2 Class I
SSTL-2 Class II
-6 Speed -7 Speed -8 Speed
Grade Grade Grade
422
390
390
422
390
390
422
390
390
422
390
390
422
390
390
250
200
200
350
300
300
350
300
300
350
300
300
350
300
300
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
4–80
Stratix Device Handbook, Volume 1
Altera Corporation
January 2006