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EPM7064STI44-7N Datasheet, PDF (42/66 Pages) Altera Corporation – Programmable Logic Device Family
MAX 7000 Programmable Logic Device Family Data Sheet
Table 29. EPM7064S External Timing Parameters (Part 2 of 2) Note (1)
Symbol
Parameter
Conditions
Speed Grade
Unit
-5
-6
-7
-10
Min Max Min Max Min Max Min Max
tACO1
tACH
tACL
tCPPW
tODH
tCNT
fCNT
tACNT
fACNT
fMAX
Array clock to output delay
C1 = 35 pF
5.4
6.7
7.5
10.0 ns
Array clock high time
2.5
2.5
3.0
4.0
ns
Array clock low time
2.5
2.5
3.0
4.0
ns
Minimum pulse width for clear (2)
and preset
2.5
2.5
3.0
4.0
ns
Output data hold time after
C1 = 35 pF (3) 1.0
1.0
1.0
1.0
ns
clock
Minimum global clock period
5.7
7.1
8.0
10.0 ns
Maximum internal global clock (4)
frequency
175.4
140.8
125.0
100.0
MHz
Minimum array clock period
5.7
7.1
8.0
10.0 ns
Maximum internal array clock (4)
frequency
175.4
140.8
125.0
100.0
MHz
Maximum clock frequency
(5)
250.0
200.0
166.7
125.0
MHz
Table 30. EPM7064S Internal Timing Parameters (Part 1 of 2) Note (1)
Symbol
Parameter
Conditions
tIN
tIO
tFIN
tSEXP
tPEXP
tLAD
tLAC
tIOE
tOD1
tOD2
tOD3
tZX1
tZX2
tZX3
tXZ
tSU
tH
Input pad and buffer delay
I/O input pad and buffer delay
Fast input delay
Shared expander delay
Parallel expander delay
Logic array delay
Logic control array delay
Internal output enable delay
Output buffer and pad delay C1 = 35 pF
Output buffer and pad delay C1 = 35 pF (6)
Output buffer and pad delay C1 = 35 pF
Output buffer enable delay C1 = 35 pF
Output buffer enable delay C1 = 35 pF (6)
Output buffer enable delay C1 = 35 pF
Output buffer disable delay C1 = 5 pF
Register setup time
Register hold time
Speed Grade
Unit
-5
-6
-7
-10
Min Max Min Max Min Max Min Max
0.2
0.2
0.5
0.5 ns
0.2
0.2
0.5
0.5 ns
2.2
2.6
1.0
1.0 ns
3.1
3.8
4.0
5.0 ns
0.9
1.1
0.8
0.8 ns
2.6
3.2
3.0
5.0 ns
2.5
3.2
3.0
5.0 ns
0.7
0.8
2.0
2.0 ns
0.2
0.3
2.0
1.5 ns
0.7
0.8
2.5
2.0 ns
5.2
5.3
7.0
5.5 ns
4.0
4.0
4.0
5.0 ns
4.5
4.5
4.5
5.5 ns
9.0
9.0
9.0
9.0 ns
4.0
4.0
4.0
5.0 ns
0.8
1.0
3.0
2.0
ns
1.7
2.0
2.0
3.0
ns
42
Altera Corporation