EPM7064STI44-7N Datasheet, PDF (37/66 Pages) Altera Corporation – Programmable Logic Device Family

MAX 7000 Programmable Logic Device Family Data Sheet
Table 25. MAX 7000 & MAX 7000E External Timing Parameters Note (1)
Symbol
Parameter
Conditions
t_PD1
t_PD2
t_SU
t_H
t_FSU
t_FH
t_CO1
t_CH
t_CL
t_ASU
t_AH
t_ACO1
t_ACH
t_ACL
t_CPPW
t_ODH
t_CNT
f_CNT
t_ACNT
f_ACNT
f_MAX
Input to non-registered output C1 = 35 pF
I/O input to non-registered
output
C1 = 35 pF
Global clock setup time
Global clock hold time
Global clock setup time of fast (2)
input
Global clock hold time of fast (2)
input
Global clock to output delay C1 = 35 pF
Global clock high time
Global clock low time
Array clock setup time
Array clock hold time
Array clock to output delay
C1 = 35 pF
Array clock high time
Array clock low time
Minimum pulse width for clear (3)
and preset
Output data hold time after
clock
C1 = 35 pF (4)
Minimum global clock period
Maximum internal global clock (5)
frequency
Minimum array clock period
Maximum internal array clock (5)
frequency
Maximum clock frequency
(6)
Speed Grade
Unit
-15
-15T
-20
Min Max Min Max Min Max
15.0
15.0
20.0 ns
15.0
15.0
20.0 ns
11.0
11.0
12.0
ns
0.0
0.0
0.0
ns
3.0
–
5.0
ns
0.0
–
0.0
ns
8.0
8.0
12.0 ns
5.0
6.0
6.0
ns
5.0
6.0
6.0
ns
4.0
4.0
5.0
ns
4.0
4.0
5.0
ns
15.0
15.0
20.0 ns
6.0
6.5
8.0
ns
6.0
6.5
8.0
ns
6.0
6.5
8.0
ns
1.0
1.0
1.0
ns
13.0
13.0
16.0 ns
76.9
76.9
62.5
MHz
13.0
13.0
16.0 ns
76.9
76.9
62.5
MHz
100
83.3
83.3
MHz
Altera Corporation
37