EP4CGX75CF23C8N Datasheet, PDF (39/42 Pages) Altera Corporation – Cyclone IV Device Datasheet

Chapter 1: Cyclone IV Device Datasheet
1–39
Glossary
Table 1–46. Glossary (Part 3 of 5)
Letter
Term
R_L
Definitions
Receiver differential input discrete resistor (external to Cyclone IV devices).
Receiver input waveform for LVDS and LVPECL differential standards:
Receiver Input
R ^Waveform
Single-Ended Waveform
V_ID
V_CM
Positive Channel (p) = V_IH
Negative Channel (n) = V_IL
Ground
Differential Waveform (Mathematical Function of Positive & Negative Channel)
Receiver input
skew margin
(RSKM)
V_ID
0V
V_ID
p-n
High-speed I/O block: The total margin left after accounting for the sampling window and TCCS.
RSKM = (TUI – SW – TCCS) / 2.
V_CCIO
V_OH
Single-ended
voltage-
referenced I/O
S _Standard
V_OL
V_REF
V_IH (AC )
V_IH(DC)
V_{IL (D C)}
VIL (AC ₎
V_SS
SW (Sampling
Window)
The JEDEC standard for SSTl and HSTL I/O standards defines both the AC and DC input signal
values. The AC values indicate the voltage levels at which the receiver must meet its timing
specifications. The DC values indicate the voltage levels at which the final logic state of the
receiver is unambiguously defined. After the receiver input crosses the AC value, the receiver
changes to the new logic state. The new logic state is then maintained as long as the input stays
beyond the DC threshold. This approach is intended to provide predictable receiver timing in the
presence of input waveform ringing.
High-speed I/O block: The period of time during which the data must be valid to capture it
correctly. The setup and hold times determine the ideal strobe position in the sampling window.
May 2013 Altera Corporation
Cyclone IV Device Handbook,
Volume 3