EPM7256AETC100-10N Datasheet, PDF (37/64 Pages) Altera Corporation – Programmable Logic Device Family

MAX 7000A Programmable Logic Device Data Sheet
Table 19. EPM7064AE External Timing Parameters Note (1)
Symbol
Parameter
Conditions
t_PD1
t_PD2
t_SU
t_H
t_FSU
t_FH
t_CO1
t_CH
t_CL
t_ASU
t_AH
t_ACO1
t_ACH
t_ACL
t_CPPW
t_CNT
f_CNT
t_ACNT
f_ACNT
Input to non-
registered output
C1 = 35 pF
(2)
I/O input to non-
registered output
C1 = 35 pF
(2)
Global clock setup (2)
time
Global clock hold time (2)
Global clock setup
time of fast input
Global clock hold time
of fast input
Global clock to output C1 = 35 pF
delay
Global clock high time
Global clock low time
Array clock setup time (2)
Array clock hold time (2)
Array clock to output C1 = 35 pF
delay
(2)
Array clock high time
Array clock low time
Minimum pulse width (3)
for clear and preset
Minimum global clock (2)
period
Maximum internal
(2), (4)
global clock frequency
Minimum array clock (2)
period
Maximum internal
(2), (4)
array clock frequency
-4
Min Max
4.5
4.5
2.8
0.0
2.5
0.0
1.0
3.1
2.0
2.0
1.6
0.3
1.0
4.3
2.0
2.0
2.0
4.5
222.2
4.5
222.2
Speed Grade
-7
Min Max
7.5
7.5
4.7
0.0
3.0
0.0
1.0
5.1
3.0
3.0
2.6
0.4
1.0
7.2
3.0
3.0
3.0
7.4
135.1
7.4
135.1
Unit
-10
Min Max
10.0 ns
10.0 ns
6.2
ns
0.0
ns
3.0
ns
0.0
ns
1.0
7.0 ns
4.0
ns
4.0
ns
3.6
ns
0.6
ns
1.0
9.6 ns
4.0
ns
4.0
ns
4.0
ns
10.0 ns
100.0
MHz
10.0 ns
100.0
MHz
Altera Corporation
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