EPM7256AETC100-10N Datasheet, PDF (20/64 Pages) Altera Corporation – Programmable Logic Device Family

MAX 7000A Programmable Logic Device Data Sheet
Table 7. MAX 7000A Stand-Alone Verification Times for Different Test Clock Frequencies
Device
EPM7032AE
EPM7064AE
EPM7128AE
EPM7256AE
EPM7512AE
EPM7128A (1)
EPM7256A (1)
10 MHz
0.00
0.01
0.01
0.02
0.03
0.08
0.13
5 MHz
0.01
0.01
0.02
0.03
0.06
0.14
0.24
2 MHz
0.01
0.02
0.04
0.08
0.15
0.29
0.54
f_TCK
1 MHz 500 kHz 200 kHz 100 kHz
0.02
0.04
0.09
0.18
0.04
0.07
0.18
0.35
0.07
0.14
0.34
0.68
0.15
0.30
0.75
1.49
0.30
0.60
1.49
2.97
0.56
1.09
2.67
5.31
1.06
2.08
5.15
10.27
50 kHz
0.36
0.70
1.36
2.98
5.94
10.59
20.51
Units
s
s
s
s
s
s
s
Note to tables:
(1) EPM7128A and EPM7256A devices can only be programmed with an adaptive algorithm; users programming these
two devices on platforms that cannot use an adaptive algorithm should use EPM7128AE and EPM7256AE devices.
Programming
with External
Hardware
MAX 7000A devices can be programmed on Windows-based PCs with an
Altera Logic Programmer card, the MPU, and the appropriate device
adapter. The MPU performs continuity checks to ensure adequate
electrical contact between the adapter and the device.
f
For more information, see the Altera Programming Hardware Data Sheet.
The Altera software can use text- or waveform-format test vectors created
with the Altera Text Editor or Waveform Editor to test the programmed
device. For added design verification, designers can perform functional
testing to compare the functional device behavior with the results of
simulation.
Data I/O, BP Microsystems, and other programming hardware
manufacturers provide programming support for Altera devices.
f ^{For more information, see Programming Hardware Manufacturers.}
IEEE Std.
1149.1 (JTAG)
Boundary-Scan
Support
MAX 7000A devices include the JTAG BST circuitry defined by IEEE Std.
1149.1. Table 8 describes the JTAG instructions supported by MAX 7000A
devices. The pin-out tables, available from the Altera web site
(http://www.altera.com), show the location of the JTAG control pins for
each device. If the JTAG interface is not required, the JTAG pins are
available as user I/O pins.
20
Altera Corporation