EPM3064ATI44-10N Datasheet, PDF (36/46 Pages) Altera Corporation – Built–in boundary-scan test circuitry compliant with

MAX 3000A Programmable Logic Device Family Data Sheet
Table 23. EPM3256A Internal Timing Parameters (Part 2 of 2) Note (1)
Symbol
Parameter
Conditions
t_ZX3
t_XZ
t_SU
t_H
t_RD
t_COMB
t_IC
t_EN
t_GLOB
t_PRE
t_CLR
t_PIA
t_LPA
Output buffer enable delay, slow C1 = 35 pF
slew rate = on
V_CCIO = 2.5 V or 3.3 V
Output buffer disable delay
C1 = 5 pF
Register setup time
Register hold time
Register delay
Combinatorial delay
Array clock delay
Register enable time
Global control delay
Register preset time
Register clear time
PIA delay
(2)
Low–power adder
(5)
Speed Grade
Unit
–7
–10
Min Max Min Max
9.0
10.0
ns
4.0
5.0
ns
2.1
2.9
ns
0.9
1.2
ns
1.2
1.6
ns
0.8
1.2
ns
1.6
2.1
ns
1.0
1.3
ns
1.5
2.0
ns
2.3
3.0
ns
2.3
3.0
ns
2.4
3.2
ns
4.0
5.0
ns
Table 24. EPM3512A External Timing Parameters Note (1)
Symbol
Parameter
Conditions
Speed Grade
Unit
-7
-10
Min Max Min Max
t_PD1
t_PD2
t_SU
t_H
t_FSU
t_FH
t_CO1
t_CH
t_CL
t_ASU
Input to non-registered output C1 = 35 pF (2)
7.5
10.0
ns
I/O input to non-registered
C1 = 35 pF (2)
7.5
output
10.0
ns
Global clock setup time
(2)
5.6
7.6
ns
Global clock hold time
(2)
0.0
0.0
ns
Global clock setup time of fast
3.0
3.0
ns
input
Global clock hold time of fast
input
0.0
0.0
ns
Global clock to output delay C1 = 35 pF
1.0
4.7
1.0
6.3
ns
Global clock high time
3.0
4.0
ns
Global clock low time
3.0
4.0
ns
Array clock setup time
(2)
2.5
3.5
ns
36
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