|
EPM3064ATI44-10N Datasheet, PDF (28/46 Pages) Altera Corporation – Built–in boundary-scan test circuitry compliant with | |||
|
◁ |
MAX 3000A Programmable Logic Device Family Data Sheet
Tables 16 through 23 show EPM3032A, EPM3064A, EPM3128A,
EPM3256A, and EPM3512A timing information.
Table 16. EPM3032A External Timing Parameters Note (1)
Symbol
Parameter
Conditions
tPD1
tPD2
tSU
tH
tCO1
tCH
tCL
tASU
tAH
tACO1
tACH
tACL
tCPPW
tCNT
fCNT
tACNT
fACNT
Input to nonâ
registered output
C1 = 35 pF
(2)
I/O input to nonâ
C1 = 35 pF
registered output
(2)
Global clock setup (2)
time
Global clock hold time (2)
Global clock to output C1 = 35 pF
delay
Global clock high time
Global clock low time
Array clock setup time (2)
Array clock hold time (2)
Array clock to output C1 = 35 pF
delay
(2)
Array clock high time
Array clock low time
Minimum pulse width (3)
for clear and preset
Minimum global clock (2)
period
Maximum internal
(2), (4)
global clock frequency
Minimum array clock (2)
period
Maximum internal
(2), (4)
array clock frequency
â4
Min Max
4.5
4.5
2.9
0.0
1.0
3.0
2.0
2.0
1.6
0.3
1.0
4.3
2.0
2.0
2.0
4.4
227.3
4.4
227.3
Speed Grade
â7
Min Max
7.5
7.5
4.7
0.0
1.0
5.0
3.0
3.0
2.5
0.5
1.0
7.2
3.0
3.0
3.0
7.2
138.9
7.2
138.9
Unit
â10
Min Max
10 ns
10 ns
6.3
ns
0.0
ns
1.0
6.7 ns
4.0
ns
4.0
ns
3.6
ns
0.5
ns
1.0
9.4 ns
4.0
ns
4.0
ns
4.0
ns
9.7 ns
103.1
MHz
9.7 ns
103.1
MHz
28
Altera Corporation
|
▷ |