EPM3064ATI44-10N Datasheet, PDF (3/46 Pages) Altera Corporation – Built–in boundary-scan test circuitry compliant with

MAX 3000A Programmable Logic Device Family Data Sheet
Table 2. MAX 3000A Speed Grades
Device
Speed Grade
–4
–5
–6
–7
–10
EPM3032A
v
EPM3064A
v
EPM3128A
v
EPM3256A
EPM3512A
v
v
v
v
v
v
v
v
v
v
The MAX 3000A architecture supports 100% transistor-to-transistor logic
(TTL) emulation and high–density small-scale integration (SSI),
medium-scale integration (MSI), and large-scale integration (LSI) logic
functions. The MAX 3000A architecture easily integrates multiple devices
ranging from PALs, GALs, and 22V10s to MACH and pLSI devices.
MAX 3000A devices are available in a wide range of packages, including
PLCC, PQFP, and TQFP packages. See Table 3.
Table 3. MAX 3000A Maximum User I/O Pins Note (1)
Device
EPM3032A
EPM3064A
EPM3128A
EPM3256A
EPM3512A
44–Pin
PLCC
34
34
44–Pin
TQFP
34
34
100–Pin 144–Pin 208–Pin 256-Pin
TQFP TQFP PQFP FineLine
BGA
66
80
96
98
116
158
161
172
208
Note:
(1) When the IEEE Std. 1149.1 (JTAG) interface is used for in–system programming or
boundary–scan testing, four I/O pins become JTAG pins.
MAX 3000A devices use CMOS EEPROM cells to implement logic
functions. The user–configurable MAX 3000A architecture accommodates
a variety of independent combinatorial and sequential logic functions.
The devices can be reprogrammed for quick and efficient iterations
during design development and debugging cycles, and can be
programmed and erased up to 100 times.
Altera Corporation
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