EPM9320LC84-15 Datasheet, PDF (33/46 Pages) Altera Corporation – Programmable Logic Device Family

MAX 9000 Programmable Logic Device Family Data Sheet
Table 22. MAX 9000 Internal Timing Characteristics
Symbol
Parameter
Conditions
t _LAD
Logic array delay
t _LAC
Logic control array delay
t_IC
Array clock delay
t _EN
Register enable time
t _SEXP
Shared expander delay
t _PEXP
Parallel expander delay
t _RD
Register delay
t _COMB
Combinatorial delay
t _SU
Register setup time
t_H
Register hold time
t _PRE
Register preset time
t _CLR
Register clear time
t_FTD
FastTrack drive delay
t _LPA
Low-power adder
(5)
Note (1)
Speed Grade
Unit
-10
-15
-20
Min Max Min Max Min Max
3.5
4.0
4.5 ns
3.5
4.0
4.5 ns
3.5
4.0
4.5 ns
3.5
4.0
4.5 ns
3.5
5.0
7.5 ns
0.5
1.0
2.0 ns
0.5
1.0
1.0 ns
0.4
1.0
1.0 ns
2.4
3.0
4.0
ns
2.0
3.5
4.5
ns
3.5
4.0
4.5 ns
3.7
4.0
4.5 ns
0.5
1.0
2.0 ns
10.0
15.0
20.0 ns
Altera Corporation
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