EPM9320LC84-15 Datasheet, PDF (1/46 Pages) Altera Corporation – Programmable Logic Device Family

June 2003, ver. 6.5
MAX 9000
Includes
®
MAX 9000A
Programmable Logic
Device Family
Data Sheet
Features...
■ High-performance CMOS EEPROM-based programmable logic
devices (PLDs) built on third-generation Multiple Array MatriX
(MAX^®) architecture
■ 5.0-V in-system programmability (ISP) through built-in IEEE Std.
1149.1 Joint Test Action Group (JTAG) interface
■ Built-in JTAG boundary-scan test (BST) circuitry compliant with IEEE
Std. 1149.1-1990
■ High-density erasable programmable logic device (EPLD) family
ranging from 6,000 to 12,000 usable gates (see Table 1)
■ 10-ns pin-to-pin logic delays with counter frequencies of up to
144 MHz
■ Fully compliant with the peripheral component interconnect Special
Interest Group’s (PCI SIG) PCI Local Bus Specification, Revision 2.2
■ Dual-output macrocell for independent use of combinatorial and
registered logic
■ FastTrack^® Interconnect for fast, predictable interconnect delays
■ Input/output registers with clear and clock enable on all I/O pins
■ Programmable output slew-rate control to reduce switching noise
■ MultiVolt^™ I/O interface operation, allowing devices to interface with
3.3-V and 5.0-V devices
■ Configurable expander product-term distribution allowing up to 32
product terms per macrocell
■ Programmable power-saving mode for more than 50% power
reduction in each macrocell
Table 1. MAX 9000 Device Features
Feature
Usable gates
Flipflops
Macrocells
Logic array blocks (LABs)
Maximum user I/O pins
t_PD1 (ns)
t_FSU (ns)
t_FCO (ns)
f_CNT (MHz)
EPM9320
EPM9320A
6,000
484
320
20
168
10
3.0
4.5
144
Altera Corporation
DS-M9000-6.5
EPM9400
8,000
580
400
25
159
15
5
7
118
EPM9480
10,000
676
480
30
175
10
3.0
4.8
144
EPM9560
EPM9560A
12,000
772
560
35
216
10
3.0
4.8
144
1