EPM240G Datasheet, PDF (33/86 Pages) Altera Corporation – MAX II Device Family

Chapter 2: MAX II Architecture
I/O Structure
2–25
Figure 2–20 shows how a row I/O block connects to the logic array.
Figure 2–20. Row I/O Block Connection to the Interconnect (Note 1)
R4 Interconnects
C4 Interconnects
I/O Block Local
Interconnect
data_out
[6..0]
7
OE
[6..0]
7
LAB
Row
fast_out
I/O Block
[6..0]
7
data_in[6..0]
7
Direct Link
Interconnect
to Adjacent LAB
LAB Local
Interconnect
Direct Link
Interconnect
from Adjacent LAB
LAB Column
clock [3..0]
Row I/O Block
Contains up to
Seven IOEs
Note to Figure 2–20:
(1) Each of the seven IOEs in the row I/O block can have one data_out or fast_out output, one OE output, and one data_in input.
© October 2008 Altera Corporation
MAX II Device Handbook