EPM240G Datasheet, PDF (14/86 Pages) Altera Corporation – MAX II Device Family

2–6
Chapter 2: MAX II Architecture
Logic Elements
Figure 2–5. LAB-Wide Control Signals
Dedicated
4
LAB Column
Clocks
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
labclkena1
labclkena2
syncload
labclr2
addnsub
labclk1
labclk2
asyncload
or labpre
labclr1
synclr
Logic Elements
The smallest unit of logic in the MAX II architecture, the LE, is compact and provides
advanced features with efficient logic utilization. Each LE contains a four-input LUT,
which is a function generator that can implement any function of four variables. In
addition, each LE contains a programmable register and carry chain with carry-select
capability. A single LE also supports dynamic single-bit addition or subtraction mode
selectable by an LAB-wide control signal. Each LE drives all types of interconnects:
local, row, column, LUT chain, register chain, and DirectLink interconnects. See
Figure 2–6.
MAX II Device Handbook
© October 2008 Altera Corporation