EPM7064QC100-15 Datasheet, PDF (31/66 Pages) Altera Corporation – Programmable Logic Device Family

MAX 7000 Programmable Logic Device Family Data Sheet
Tables 19 through 26 show the MAX 7000 and MAX 7000E AC
operating conditions.
Table 19. MAX 7000 & MAX 7000E External Timing Parameters Note (1)
Symbol
Parameter
Conditions
t_PD1
t_PD2
t_SU
t_H
t_FSU
t_FH
t_CO1
t_CH
t_CL
t_ASU
t_AH
t_ACO1
t_ACH
t_ACL
t_CPPW
t_ODH
t_CNT
f_CNT
t_ACNT
f_ACNT
f_MAX
Input to non-registered output
I/O input to non-registered output
Global clock setup time
Global clock hold time
Global clock setup time of fast input
Global clock hold time of fast input
Global clock to output delay
Global clock high time
Global clock low time
Array clock setup time
Array clock hold time
Array clock to output delay
Array clock high time
Array clock low time
Minimum pulse width for clear and
preset
Output data hold time after clock
Minimum global clock period
Maximum internal global clock
frequency
Minimum array clock period
Maximum internal array clock
frequency
Maximum clock frequency
C1 = 35 pF
C1 = 35 pF
(2)
(2)
C1 = 35 pF
C1 = 35 pF
(3)
C1 = 35 pF (4)
(5)
(5)
(6)
-6 Speed Grade
Min Max
6.0
6.0
5.0
0.0
2.5
0.5
4.0
2.5
2.5
2.5
2.0
6.5
3.0
3.0
3.0
1.0
6.6
151.5
6.6
151.5
200
-7 Speed Grade
Min Max
7.5
7.5
6.0
0.0
3.0
0.5
4.5
3.0
3.0
3.0
2.0
7.5
3.0
3.0
3.0
1.0
8.0
125.0
8.0
125.0
166.7
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
ns
MHz
MHz
Altera Corporation
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