EPM7064QC100-15 Datasheet, PDF (3/66 Pages) Altera Corporation – Programmable Logic Device Family

General
Description
MAX 7000 Programmable Logic Device Family Data Sheet
■ Additional design entry and simulation support provided by EDIF
2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM),
Verilog HDL, VHDL, and other interfaces to popular EDA tools from
manufacturers such as Cadence, Exemplar Logic, Mentor Graphics,
OrCAD, Synopsys, and VeriBest
■ Programming support
– Altera’s Master Programming Unit (MPU) and programming
hardware from third-party manufacturers program all
MAX 7000 devices
– The BitBlaster^TM serial download cable, ByteBlasterMV^TM
parallel port download cable, and MasterBlaster^TM
serial/universal serial bus (USB) download cable program MAX
7000S devices
The MAX 7000 family of high-density, high-performance PLDs is based
on Altera’s second-generation MAX architecture. Fabricated with
advanced CMOS technology, the EEPROM-based MAX 7000 family
provides 600 to 5,000 usable gates, ISP, pin-to-pin delays as fast as 5 ns,
and counter speeds of up to 175.4 MHz. MAX 7000S devices in the -5, -6,
-7, and -10 speed grades as well as MAX 7000 and MAX 7000E devices in
-5, -6, -7, -10P, and -12P speed grades comply with the PCI Special Interest
Group (PCI SIG) PCI Local Bus Specification, Revision 2.2. See Table 3
for available speed grades.
Table 3. MAX 7000 Speed Grades
Device
-5
-6
-7
EPM7032
v
v
EPM7032S v
v
v
EPM7064
v
v
EPM7064S v
v
v
EPM7096
v
EPM7128E
v
EPM7128S
v
v
EPM7160E
EPM7160S
v
v
EPM7192E
EPM7192S
v
EPM7256E
EPM7256S
v
Speed Grade
-10P -10 -12P -12
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
-15 -15T -20
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
Altera Corporation
3