ER3125QI Datasheet, PDF (3/30 Pages) Altera Corporation – MOSFET for Synchronous Buck or Boost Buck Converter

Page 3
Functional Pin Descriptions (Continued)
PIN NAME PIN #
DESCRIPTION
LLM
7 Light load mode selection pin. Pull this pin to GND for forced PWM mode; to have it floating or connected to AVINO will enable LLM mode
when the peak inductor current is below the default threshold of 700mA. The current boundary threshold between LLM and PWM can also be
programmed with a resistor at this pin to ground. Check for more details in the “LLM Mode Operation” on page 15.
POK
8 POK is an open drain output and pull-up pin with a resistor to AVINO for proper function. POK will be pulled low under the events when the
output is out of regulation (OV or UV) or EN pin is pulled low. POK rising has a fixed 128 cycles delay.
SW
9, 10 These pins are the SW nodes that should be connected to the output inductor. These pins are connected to the source of the high-side N-
channel MOSFET.
BOOST
11 This pin is used to set boost mode and monitor the battery voltage that is the input of the boost converter. After AVINO POR, the controller will
detect the voltage on this pin; if voltage on this pin is below 200mV, the controller is set in synchronous/non-synchronous buck mode and will
latch in this state unless AVINO is below POR falling threshold; if the voltage on this pin after AVINO POR is above 200mV, the controller is set
in boost mode and latches in this state. In boost mode, the low-side driver output PWM with same duty cycle with upper-side driver to drive
the boost switch.
In boost mode, this pin is used to monitor input voltage through a resistor divider. By setting the resistor divider, the high threshold and
hysteresis can be programmed. When voltage on this pin is above 0.8V, the PWM output (LGATE) for the boost converter is disabled, and when
voltage on this pin is below 0.8V minus the hysteresis, the boost PWM is enabled.
In boost mode operation, LLM is disabled when boost PWM is enabled. Check the “2-Stage Boost Buck Converter Operation” on page 17 for
more details.
SYNC
12 This pin can be used to synchronize two or more ER3125QI controllers. Multiple ER3125QIs can be synchronized with their SYNC pins
connected together. 180° phase shift is automatically generated between the master and slave ICs.
The internal oscillator can also lock to an external frequency source applied on this pin with square pulse waveform (with frequency 10% higher
than the IC’s local frequency, and pulse width higher than 150ns). Range: 0V to 5.5V.
This pin should be left floating if not used.
LGATE
13 In synchronous buck mode, this pin is used to drive the lower side MOSFET to improve efficiency. A 5.1k or smaller value resistor has to be
added to connect LGATE to ground to avoid falsely turn-on of LGATE caused by coupling noise.
In non-synchronous buck when a diode is used as the bottom side power device, this pin should be connected to AVINO through a resistor
(less than 5k) before IC start-up to have the low-side driver (LGATE) disabled.
In boost mode, it can be used to drive the boost power MOSFET. The boost control PWM is same with the buck control PWM.
PGND
14 This pin is used as the ground connection of the power flow including driver. Connect it to large ground plane.
BOOT
15 This pin provides bias voltage to the high-side MOSFET driver. A bootstrap circuit is used to create a voltage suitable to drive the internal N-
channel MOSFET. The boot charge circuitries are integrated inside of the IC. No external boot diode is needed. A 1µF ceramic capacitor is
recommended to be used between BOOT and SW pin.
PVIN
16, 17 Connect the input rail to these pins that are connected to the drain of the integrated high-side MOSFET as well as the source for the internal
linear regulator that provides the bias of the IC. Range: 3V to 36V.
With the part switching, the operating input voltage applied to the PVIN pins must be under 36V. This recommendation allows for short voltage
ringing spikes (within a couple of ns time range) due to switching while not exceeding “Absolute Maximum Ratings” on page 5.
AGND
18 This pin provides the return path for the control and monitor portions of the IC. Connect it to a quiet ground plane.
AVINO
19 This pin is the output of the internal linear regulator that supplies the bias for the IC including the driver. A minimum 4.7µF decoupling ceramic
capacitor is recommended between AVINO to ground.
AVIN
20 This pin is the input of the auxiliary internal linear regulator, which can be supplied by the regulator output after power-up. With such
configuration, the power dissipation inside of the IC is reduced. The input range for this LDO is 3V to 20V.
In boost mode operation, this pin works as boost output overvoltage detection pin. It detects the boost output through a resistor divider. When
voltage on this pin is above 0.8V, the boost PWM is disabled; and when voltage on this pin is below 0.8V minus the hysteresis, the boost PWM
is enabled.
Range: 0V to 20V.
PAD
21 Bottom thermal pad. It is not connected to any electrical potential of the IC. In layout it must be connected to PCB ground copper plane with
area as large as possible to effectively reduce the thermal impedance.
May 2014 Altera Corporation
10040
Enpirion Power Datasheet ER3125QI 2.5A Regulator with Integrated High-Side MOSFET for
Synchronous Buck or Boost Buck Converter
May 28, 2014
Rev A