ER3125QI Datasheet, PDF (20/30 Pages) Altera Corporation – MOSFET for Synchronous Buck or Boost Buck Converter

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f_SW (kHz)
FIGURE 28. R_FSW vs FREQUENCY
The SYNC pin is bi-directional and it outputs the IC’s default or programmed local clock signal when it’s free running.
The IC locks to an external clock injected to the SYNC pin (external clock frequency recommended to be 10% higher
than the free running frequency). The delay from the rising edge of the external clock signal to the SW rising edge is half of
the free running switching period pulse 220ns, (0.5Tsw+220ns). The maximum external clock frequency is recommended to
be 1.6 of the free running frequency.
When the part enters LLM pulse skipping mode, the synchronization function is shut off and also no clock signal
output in SYNC pin.
With the SYNC pins simply connected together, multiple ER3125QIs can be synchronized. The slave ICs automatically
have 180° phase shift with respective to the master IC.
POK
The POK pin is output of an open drain transistor (refer to at “Block Diagram” on page 14). An external resistor is
required to be pulled up to AVINO for proper POK function. At start-up, POK will be turned HIGH (internal POK
open drain transistor is turned off) with 128 cycles delay after soft-start is finished (soft-start ramp reaches 1.02V) and
FB voltage is within OV/UV window (90%REF < FB < 110%REF).
At normal operation, POK will be pulled low with 1 cycle (minimum) and 6 cycles (maximum) delay if any of the OV
(110%) or UV (90%) comparator is tripped. The POK will be released HIGH with 128 cycles delay after FB recovers to
be within OV/UV window (90%REF < FB < 110%REF). When EN is pulled low or AVINO is below POR, POK is
pulled low with no delay.
In the case when the POK pin is pulled up by external bias supply instead of AVINO of itself, when the part is
disabled, the internal POK open drain transistor is off, the external bias supply can charge POK pin HIGH. This should
be known as false POK reporting. At start-up when AVINO rise from 0, POK will be pulled low when AVINO reaches
1V. After EN is pulled low and AVINO is falling, the POK internal open drain transistor will open with high
impedance when AVINO falls below 1V. The time between EN pulled low and POK OPEN depends on the AVINO
falling time to 1V.
Fault Protection
Overcurrent Protection
The overcurrent function protects against any overload condition and output short at worst case, by monitoring the
current flowing through the upper MOSFET.
There are 2 current limiting thresholds. The first one I_OC1 is to limit the high-side MOSFET peak current cycle-by-cycle.
The current limit threshold is set to default at 3.6A with RCLX pin connected to GND or AVINO, or left open. The
current limit threshold can also be programmed by a resistor R_CLX at RCLX pin to ground. Use Equation 14 to calculate
the resistor.
R_CLX = -I-_O----_C---_[-3--A-0---_]^{0---0+---0--0-0--.-0---1---8--}
(EQ. 14)
Enpirion Power Datasheet ER3125QI 2.5A Regulator with Integrated High-Side MOSFET for
Synchronous Buck or Boost Buck Converter
10040
May 28, 2014
May 2014 Altera Corporation
Rev A