ER3125QI Datasheet, PDF (26/30 Pages) Altera Corporation – MOSFET for Synchronous Buck or Boost Buck Converter

Page 26
The compensator design procedure is as follows:
1. Position ω_CZ2 and ω_CP to derive R₃ and C₃.
Put the compensator zero ω_CZ2 at (1 to 3)/(R_oC_o)
ω_cz2 = _R----o--3--C---_o-
(EQ. 30)
Put the compensator pole ω_CP at ESR zero or 0.35 to 0.5 times of switching frequency, whichever is lower. In all-ceramic-cap
design, the ESR zero is normally higher than half of the switching frequency. R₃ and C₃ can be derived as follows:
Case A: ESR zero -2---_π----R-1--_c---C----_o- less than (0.35 to 0.5)f_SW
C₃ = ^R----o----C---^o--3--^–--R---3-₁--R----^c---C---^o-
(EQ. 31)
Case B: ESR zero -2---_π----R-1--_c---C----_o- larger than (0.35 to 0.5)f_SW
R₃ = _R---3-o---R-_–---^c--3R---R-¹---_c-
(EQ. 32)
C₃ = ^{0----.-3---3----R---o}---fC-_S---^o-_W--f--^S-R--^W--₁----^–-----0---.-4---6--
R₃ = -0---.-7---3---R----_o---C-R---_o-¹--f--_S---_W------_–-----1-
(EQ. 33)
(EQ. 34)
2. Derive R₂ and C₁.
The loop gain L_v(S) at cross over frequency of f_c has unity gain. Therefore, C₁ is determined by Equation 35.
C₁ = -⁽_2--R-π---¹-f--_c-⁺-R----R_t--R--³--₁-⁾--CC----_o3-
(EQ. 35)
The compensator zero ω_CZ1 can boost the phase margin and bandwidth. To put ω_CZ1 at 2 times of cross cover frequency f_c is a
good start point. It can be adjusted according to specific design. R₁ can be derived from Equation 36.
R₂ = _4----π---f-1-_c---C----₁-
(EQ. 36)
Example: V_PVIN = 12V, V_o = 5V, I_o = 2A, f_SW = 500kHz, C_o = 60µF/3mΩ, L = 10µH, R_t = 0.20V/A, f_c = 50kHz, R₁ = 105k,
R_BIAS = 20kΩ.
Select the crossover frequency to be 35kHz. Since the output capacitors are all ceramic, use Equations 33 and 34 to derive R₃ to
be 20k and C₃ to be 470pF.
Then use Equations 35 and 36 to calculate C1 to be 180pF and R₂ to be 12.7k. Select 150pF for C₁ and 15k for R₂.
There is approximately 30pF parasitic capacitance between COMP to FB pins that contributes to a high frequency pole. Any extra
external capacitor is not recommended between COMP and FB.
Figure 32 shows the simulated bode plot of the loop. It is shown that it has 26kHz loop bandwidth with 70° phase margin and -
28 dB gain margin.
Note in applications where the LLM mode is desired especially when type III compensation network is used, the value
of the capacitor between the COMP pin and the FB pin (not the capacitor in series with the resistor between COMP
and FB) should be minimal to reduce the noise coupling for proper LLM operation. No external capacitor between
COMP and FB is recommended at LLM applications.
In LLM mode operations, a RC filter from FB to ground (R in series with C, connecting from FB to ground) may help to
reduce the noise effects injected to FB pin. The recommended values for the filter is 499Ω to 1k for the R and 470pF for
the C.
Enpirion Power Datasheet ER3125QI 2.5A Regulator with Integrated High-Side MOSFET for
Synchronous Buck or Boost Buck Converter
10040
May 28, 2014
May 2014 Altera Corporation
Rev A