EP220 Datasheet, PDF (3/16 Pages) Altera Corporation – Classic EPLDs

Altera Corporation
EP220 & EP224 Classic EPLDs
Figure 1. EP220 & EP224 Block Diagram
Numbers in parentheses refer to the pin-out number.
EP220
Global Clock
INPUT/CLK (1)
INPUT (2)
INPUT (3)
INPUT (4)
INPUT (5)
INPUT (6)
INPUT (7)
INPUT (8)
INPUT (9)
INPUT (11)
Global
Bus
Macrocell 1
Macrocell 2
Macrocell 3
Macrocell 4
Macrocell 5
Macrocell 6
Macrocell 7
Macrocell 8
I/O (19)
I/O (18)
I/O (17)
I/O (16)
I/O (15)
I/O (14)
I/O (13)
I/O (12)
EP224
INPUT/CLK (1)
INPUT (2)
INPUT (3)
INPUT (4)
INPUT (5)
INPUT (6)
INPUT (7)
INPUT (8)
INPUT (9)
INPUT (10)
INPUT (11)
INPUT (13)
INPUT (14)
INPUT (23)
Global Clock
Global
Bus
Macrocell 1
Macrocell 2
Macrocell 3
Macrocell 4
Macrocell 5
Macrocell 6
Macrocell 7
Macrocell 8
I/O (22)
I/O (21)
I/O (20)
I/O (19)
I/O (18)
I/O (17)
I/O (16)
I/O (15)
The EP220 and EP224 architecture is based on a sum-of-products,
programmable-AND/fixed-OR structure. Each macrocell can be
individually programmed for combinatorial or registered output. An
inversion option allows each output to be configured for active-high or
active-low operation. Each I/O pin can be programmed to function as an
input, output, or bidirectional pin.
The EP220 and EP224 device architecture offers the following features:
s Macrocells
s High-frequency, low-skew global Clock
3