EP3C5E144C7N Datasheet, PDF (29/34 Pages) Altera Corporation – 1. Cyclone III Device Datasheet

Chapter 1: Cyclone III Device Datasheet
Glossary
1–29
Table 1–39. Glossary (Part 3 of 5)
Letter
Term
Definitions
V_CCIO
V_OH
Single-ended
Voltage
referenced I/O
S _Standard
V_OL
V_REF
V_IH (AC )
V_IH(DC)
V_{IL (D C)}
VIL (AC ₎
V_SS
The JEDEC standard for SSTl and HSTL I/O standards defines both the AC and DC input signal
values. The AC values indicate the voltage levels at which the receiver must meet its timing
specifications. The DC values indicate the voltage levels at which the final logic state of the
receiver is unambiguously defined. After the receiver input crosses the AC value, the receiver
changes to the new logic state. The new logic state is then maintained as long as the input stays
beyond the DC threshold. This approach is intended to provide predictable receiver timing in the
presence of input waveform ringing.
SW (Sampling
Window)
HIGH-SPEED I/O Block: The period of time during which the data must be valid to capture it
correctly. The setup and hold times determine the ideal strobe position in the sampling window.
t_C
TCCS (Channel-
to-channel-skew)
tcin
High-speed receiver/transmitter input and output clock period.
HIGH-SPEED I/O Block: The timing difference between the fastest and slowest output edges,
including t_CO variation and clock skew. The clock is included in the TCCS measurement.
Delay from clock pad to I/O input register.
t_CO
tcout
Delay from clock pad to I/O output.
Delay from clock pad to I/O output register.
t_DUTY
HIGH-SPEED I/O Block: Duty cycle on high-speed transmitter output clock.
T
t_FALL
t_H
Signal High-to-low transition time (80–20%).
Input register hold time.
Timing Unit
HIGH-SPEED I/O block: The timing budget allowed for skew, propagation delays, and data
Interval (TUI)
sampling window. (TUI = 1/(Receiver Input Clock Frequency Multiplication Factor) = t_C/w).
t_INJITTER
Period jitter on PLL clock input.
t_{OUTJITTER_DEDCLK} Period jitter on dedicated clock output driven by a PLL.
t_{OUTJITTER_IO}
Period jitter on general purpose I/O driven by a PLL.
tpllcin
Delay from PLL inclk pad to I/O input register.
tpllcout
Delay from PLL inclk pad to I/O output register.
July 2012 Altera Corporation
Cyclone III Device Handbook
Volume 2