EP3C5E144C7N Datasheet, PDF (24/34 Pages) Altera Corporation – 1. Cyclone III Device Datasheet

1–24
Chapter 1: Cyclone III Device Datasheet
Switching Characteristics
Table 1–33. Cyclone III Devices Transmitter Channel-to-Channel Skew (TCCS) – Write Side ⁽¹⁾ (Part 2 of 2)
Memory
Standard
I/O Standard
DDR2 SDRAM
DDR SDRAM
QDRII SRAM
SSTL-18 Class I
SSTL-18 Class II
SSTL-2 Class I
SSTL-2 Class II
1.8 V HSTL Class I
1.8 V HSTL Class II
DDR2 SDRAM
DDR SDRAM
QDRII SRAM
SSTL-18 Class I
SSTL-18 Class II
SSTL-2 Class I
SSTL-2 Class II
1.8 V HSTL Class I
1.8 V HSTL Class II
DDR2 SDRAM
DDR SDRAM
QDRII SRAM
SSTL-18 Class I
SSTL-18 Class II
SSTL-2 Class I
SSTL-2 Class II
1.8 V HSTL Class I
1.8 V HSTL Class II
DDR2 SDRAM
(2)
DDR SDRAM
QDRII SRAM
SSTL-18 Class I
SSTL-18 Class II
SSTL-2 Class I
SSTL-2 Class II
1.8 V HSTL Class I
1.8 V HSTL Class II
Column I/Os (ps)
Lead
Lag
915
410
1025
545
880
340
1010
380
910
450
1010
570
C8
1040
440
1180
600
1010
360
1160
410
1040
490
1190
630
I7
961
431
1076
572
924
357
1061
399
956
473
1061
599
A7
1092
462
1239
630
1061
378
1218
431
1092
515
1250
662
Row I/Os (ps)
Lead
Lag
915
410
1025
545
880
340
1010
380
910
450
1010
570
Wraparound Mode (ps)
Lead
Lag
1015
510
1125
645
980
440
1110
480
1010
550
1110
670
1040
440
1140
540
1180
600
1280
700
1010
360
1110
460
1160
410
1260
510
1040
490
1140
590
1190
630
1290
730
961
431
1061
531
1076
572
1176
672
924
357
1024
457
1061
399
1161
499
956
473
1056
573
1061
599
1161
699
1092
462
1192
562
1239
630
1339
730
1061
378
1161
478
1218
431
1318
531
1092
515
1192
615
1250
662
1350
762
Notes to Table 1–33:
(1) Column I/O banks refer to top and bottom I/Os. Row I/O banks refer to right and left I/Os. Wraparound mode refers to the combination of column
and row I/Os.
(2) For DDR2 SDRAM write timing performance on Columns I/O for C8 and A7 devices, 97.5 degree phase offset is required.
Table 1–34 lists the memory output clock jitter specifications for Cyclone III devices.
Table 1–34. Cyclone III Devices Memory Output Clock Jitter Specifications ^{(1), (2)} (Part 1 of 2)
Parameter
Clock period jitter
Cycle-to-cycle period jitter
Symbol
t_JIT(per)
t_JIT(cc)
Min
Max
Unit
-125
125
ps
-200
200
ps
Cyclone III Device Handbook
Volume 2
July 2012 Altera Corporation